TSMC 130nm process
Cadence design with TSMC 130nm process
This tutorial will start from very basics in analog IC design then take you through the whole analog IC design process.
Here is the outline of the analog IC design flow:
- Schematic capture (Cadence tool)
- Netlist extraction from schematic
- Simulating using ELDO simulator and viewing results with EZWAVE (ELDO is a Mentor Graphic's tool for netlist level simulations)
- Layout using Cadence
- Signoff layout (DRC, LVS and parasitic extraction) using Calibre (Calibre is a Mentor Graphic's tool)
Setup of Cadence
To start virtuoso one must first connect to mikroserver3
ssh -X mikroserver3
First time you should add the following line to your cds.lib-file by running this command:
mkdir ~/tsmc echo "DEFINE tsmc13rf /eda/design_kits/tsmc_013/tsmc13rf" > ~/tsmc/cds.lib
Then (each time) run these commands to set up Cadence
source /eda/cadence/2016-17/scripts/analog_flow.sh source /eda/cadence/eda_general_init.sh
Virtuoso Mixed Signal Design Environment is started by issuing this command:
- Make sure you source the script from the correct year. I.e 2016-17 and not 2015-16
- Make sure you are connected the the right mikroserver
- Make sure you run virtuoso from the same folder as your 'cds.lib'-folder ('~/tsmc/')
In the log window, choose "File > New > Library".
In the "New Library" dialog box, you must give the library a name (for example TORLIB, as I did). You must also specify a technology file. Here you choose "Attach to an existing technology library". Then click the OK button. When asked for technology, choose "tsmc13rf".
After successfully creating the new library, it is time to create your first design. In the log window, choose "File > New > Cellview". In the "Create New File" dialog box, you must give the design a name. You must also specify which library the design belongs to, and here you specify the library that you have just created. Choose to open the cell with "Schematics XL" and add a check-mark to always use this application if it is not checked.
Now click OK, and the Virtuoso Schematic Editor should pop up. We will now draw a simple inverter design, as shown in the picture:
Entering the design
To create the inverter design, do the following:
- Press 'i' or click on the "Instance" icon to invoke the transistors. The "Add Instance" dialog box will now pop up. In the "Library" field, click "Browse" to open the "Library Browser". In the library browser, choose "tsmc13rf" as library, "nmos3v" (for n-type transistor) or "pmos3v" (for p-type transistor) as cell and "spectre" as view. The cell is placed in the schematic by moving the cursor to the desired location and clicking the left mouse button.
- To insert the voltage sources, pick the "vdc" cell from the "analogLib" library. Add one connected to vdd and gnd and one connected to the input.
- To insert the ground and vdd nets, pick the "vdd" and "gnd" cells from the "analogLib" library. Here the view name should be "symbol", not "spectreS" (in fact, "symbol" is the only available option).
- To connect the symbols, press 'w' or click the "Wire (narrow)" icon. Then use the left mouse button to click the nodes togeter, two by two.
- To remove an instance or a wire, left click at the instance or wire that you want to remove, then press the "Delete" button on the keyboard.
- To insert a pin, press 'p'. Choose a name for the pin in the dialog that occurs and click on the schematic to place it. Create one input and one output.
- To change the properties of the icons, press 'q' or click at the "Properties" icon. Then click at the instances or nets that you want to modify. For the vdc source connected between vdd and gnd, set the "DC voltage" property to 3.3.
- To check and save the schematic, press 'x' or click the "Check and save" icon.
- If there are any errors or warnings, press ok and press 'g' or "Check->Find Marker" to view the errors. Make sure you have no errors or warnings before continuing.
Simulating the design
- Open "Launch > ADE GXL" and press create new view. The "Virtuoso Analog Environment" should now come up.
- Choose "Create > Test..." select the cell to simulate.
- Choose "Outputs > To be plotted > Select on Schematic". Click at the "in" node connected to the inverter input and the "out" node connected to the output.
- Choose "Analyses > Choose". We will now run a dc analysis to obtain the DC transfer characteristics of the inverter. Choose "Component parameter" as your sweep variable. Then click at "Select component". In the schematic, click at the input "vdc" instance. In the "Select Component Parameter" dialog box, choose dc as your sweep parameter. The sweep range should go from 0 to 3.3.
- Switch to the "adexl" tab and choose the green run button. When the run is completed press the graph button beside the box that says "Replace". The outputs should look like this:
To save your simulation settings, choose "Session > Save state" in the test editor windoe to save your state information under whatever file name you want. In a later session, you can reload your saved states using "Session > Load state".
Generating a Symbol
Finally, we want to generate a symbol for our inverter. This symbol is needed if we want to use our inverter design inside another design (hierarchical design methodology).
Select the schematic tab and choose "Create -> Create Cellview -> From Cellview".
Press OK in the dialog that occurs.
The pins should already be connected to the right positions in the symbol generator, so press OK here also and ths symbol editor will occur.
Press the red X and delete the pre-created green square. Use the line tool and the circle tool to create the inverter symbol
Save it by clicking the "Save and check" symbol or pressing 'shift+X'.