User contributions for Put009
6 November 2018
- 09:5009:50, 6 November 2018 diff hist +49 m TSMC 130nm process Added if IHP are used, use SG13_dev technology current
4 May 2018
- 15:4715:47, 4 May 2018 diff hist +2,472 Layout XL and IHP SG13S Added Parasitic extraction QRC and Post Layout Simulation
- 15:2815:28, 4 May 2018 diff hist 0 N File:Hierarchy editor.png No edit summary current
- 15:0015:00, 4 May 2018 diff hist 0 N File:LVS summary.png No edit summary current
- 11:4311:43, 4 May 2018 diff hist 0 N File:Extracted layout SRAM with bt wd.png No edit summary current
3 May 2018
- 08:5208:52, 3 May 2018 diff hist 0 N File:ASSURA QRC.png No edit summary current
21 April 2018
- 17:1717:17, 21 April 2018 diff hist +112 m MikroserverSetup Added command for copying folders
- 17:0117:01, 21 April 2018 diff hist +530 Cadence Testbench Added simulation procedure current
11 April 2018
- 13:3313:33, 11 April 2018 diff hist +2 m TSMC 130nm process No edit summary
- 11:4611:46, 11 April 2018 diff hist −5 m TSMC 130nm process Moved launch ade gxl from entering to simulation
13 March 2018
- 12:3812:38, 13 March 2018 diff hist +144 m Modelsim/Questa Updated a dead link
12 March 2018
- 14:1414:14, 12 March 2018 diff hist +103 m Synthese av VHDL - Oppdatert Link til intel si nedlastingsside for quartus og modelsim current
- 11:4911:49, 12 March 2018 diff hist +264 m XJTAG Updated path to XJTAG 3.5
8 March 2018
- 13:1813:18, 8 March 2018 diff hist +45 m Bitvis UVVM VHDL Verification Component Framework Corrected write and read signal names in set_inputs_passive and fixed dead link