User contributions
From ift
- 14:44, 5 February 2021 diff hist +13 m Synthese av VHDL oppdatert sdf-inkludering med sdfnoerror current
- 13:10, 5 February 2021 diff hist +278 m Synthese av VHDL →Koden til alu_tb.vhdl
- 09:05, 5 February 2021 diff hist 0 m Synthese av VHDL →Precision
- 22:13, 4 February 2021 diff hist -16 m Modelsim/Questa →Referanselitteratur current
- 22:09, 4 February 2021 diff hist +2 m VHDL Testbenk →Do-file og testbenk current
- 22:08, 4 February 2021 diff hist -14 m VHDL Testbenk
- 22:06, 4 February 2021 diff hist +13 m Simulering av VHDL →Starte Questa Sim current
- 22:05, 4 February 2021 diff hist +1 m Synthese av VHDL
- 22:02, 4 February 2021 diff hist -383 Modelsim/Questa
- 14:48, 4 February 2021 diff hist +4 m Synthese av VHDL
- 14:46, 4 February 2021 diff hist +2 m Synthese av VHDL →Precision
- 14:39, 4 February 2021 diff hist -20 m Synthese av VHDL
- 14:37, 4 February 2021 diff hist -165 m Synthese av VHDL
- 13:52, 4 February 2021 diff hist +496 Synthese av VHDL Updated to Vivado
- 12:30, 15 October 2020 diff hist +3 m IHP 130nm process
- 10:20, 15 October 2020 diff hist +220 m IHP 130nm process
- 10:19, 15 October 2020 diff hist -2 m Layout XL and IHP SG13S
- 09:32, 15 October 2020 diff hist +26 m IHP 130nm process
- 09:07, 15 October 2020 diff hist 0 m Layout XL and IHP SG13S
- 08:58, 15 October 2020 diff hist -1 m IHP 130nm process Updated to new software distro and design kit
- 12:39, 23 September 2020 diff hist +506 m Symbolsk løsning av nodeligninger med Matlab Added calculation for all capacitors current
- 12:13, 23 September 2020 diff hist -5 m Symbolsk løsning av nodeligninger med Matlab
- 12:02, 23 September 2020 diff hist -35 m Symbolsk løsning av nodeligninger med Matlab Updated for newer Matalb versions (tested on R2020b)
- 14:37, 7 September 2020 diff hist +113 m PHYS222 →Prosessteknologi current
- 14:33, 7 September 2020 diff hist +79 m PHYS222 →Prosessteknologi
- 14:26, 7 September 2020 diff hist +63 m PHYS222 →Prosessteknologi
- 15:11, 18 August 2020 diff hist +66 m Microelectronics group current
- 15:07, 18 August 2020 diff hist +119 m Microelectronics group
- 09:21, 30 March 2020 diff hist +35 m SSH tunnel current
- 09:10, 30 March 2020 diff hist -25 m IHP 130nm process
- 08:54, 30 March 2020 diff hist -227 m MikroserverSetup Removed full path references
- 15:54, 2 March 2020 diff hist -132 m PHYS321 →Nettressurser current
- 15:45, 2 March 2020 diff hist +97 m PHYS222 →Prosessteknologi
- 15:41, 2 March 2020 diff hist +95 m PHYS222 →Prosessteknologi
- 13:54, 31 January 2020 diff hist +5 m VHDL Testbenk →Do-file og testbenk
- 13:53, 31 January 2020 diff hist +58 m VHDL Testbenk →Do-file og testbenk
- 13:51, 31 January 2020 diff hist 0 m Simulering av VHDL →Starte Questa Sim
- 16:19, 30 January 2020 diff hist +5 m Synthese av VHDL →Modelsim
- 14:59, 30 January 2020 diff hist +30 m Simulering av VHDL →Signaler og variable
- 14:57, 30 January 2020 diff hist +141 m Simulering av VHDL →Signaler og variable
- 15:51, 4 November 2019 diff hist -5 m MikroserverSetup
- 11:18, 4 November 2019 diff hist -5 m IHP 130nm process
- 10:01, 4 November 2019 diff hist 0 m IHP 130nm process
- 10:01, 4 November 2019 diff hist 0 m IHP 130nm process
- 14:06, 23 January 2019 diff hist +9 m Modelsim/Questa Oppdatert til bitvis UVVM
- 13:07, 30 October 2018 diff hist +7 m Gitlab Changed from gitlab to git.app current
- 10:10, 13 September 2018 diff hist -17 m PHYS222
- 09:52, 13 September 2018 diff hist +2 m PHYS222
- 09:49, 13 September 2018 diff hist -25 m PHYS222
- 09:24, 23 August 2018 diff hist +71 m PHYS222
