Laboratory exercise for building and running the HLT-RORC hardware/software
Simulation in ModelSim
1. Extract "HLT-RORC.ZIP", file:/heim/torheim/arkiv/HLT-RORC.ZIP into your working directory.
2. Set environment variable PROJECT_PATH equal to /my_working_directory/HLT-RORC/modelsim.
3. Start modelsim, then open project file HLT-prosjektfil.mpf in directory HLT-RORC/modelsim.
4. Map the simulation libraries. You can do this by typing from the command line (in the following order):
vlib work # Creating the work library vmap altera_pci /pakke/mgc/altera/vhdl/altera_pci vmap lpm /pakke/mgc/altera/vhdl/220model vmap altera_mf /pakke/mgc/altera/vhdl/altera_mf
If the compiled simulation libraries have become obsolete, you will have to compile the libraries yourself. This can be done by typing (in the following order):
vcom –work altera_mf altera_mf_components.vhd vcom –work altera_mf altera_mf.vhd vcom –work lpm 220pack.vhd vcom –work lpm 220model.vhd
5. The mstr_tranx.vhd module contains the master transactions controlling the simulation scenario. To run the simulation with interrupt transfers, set the variable int_or_not equal to 1. To run the simulation with DMA transfers only, set the variable to zero.
6.Now you should compile your testbench with the design into your library work. The testbench could then be loaded by typing vsim -t ps work.testbench from the !ModelSim command line (not specifying the resolution in ps will result in a a fatal error). To run the simulation with 32 bit PCI bus, you could simply type force -freeze /testbench/ack64n 1 before running simulation.
7. Run the simulation by typing run ![time in ns].
(You can get rid of all the warnings if you choose Simulate -> Simulation Options -> Assertions -> Ignore assertions for warning from the menu line)
Synthesizing, technology mapping and transferring the design onto the APEX20KE FPGA
1. Open Precision RTL Synthesis. Choose File -> New Project. Set the working directory to whatever you want to.
2. Add all the required VHDL files to you project. Make sure local_side.vhd is the last added file (The last added file will automatically be set as top of design).
3. Choose Setup Design to set the following options: APEX 20KE as technology, EP20K400EFC672 as device and -2X for the speed grade. The design frequency shold be 40 !MHz.
4. Click Compile, followed by Synthesize.
5. Close Precision RTL Synthesis. Make sure to anser "Yes" when asked about saving the current implementation.
6. A subdirectory called local_side_impl_1 has now been created in your working directory. Copy the content of local_side_impl_1 to /your_working_directory/HLT-RORC/LS/run_1. Answer yes when questioned to overwrite existing data.
7. Open top_module.qpf from Quartus. Convert the project file to the new Quartus file format if asked to do so.
8. If necessary, choose Tools -> !SignalTap Logic Analyzer and update the SignalTap file to the new file format.
9.Choose Assigments -> Settings -> User Library and add the correct library path (your_working_directory\HLT-RORC\pci_compiler-v2.1.1\lib). The newer versions of the pci core cannot be used, since the APEX20KE has been abandoned from further development.
10. Choose Processing -> Start Compilation to compile the design (this will take some time).
11. Choose Tools -> Programmer. Now choose JTAG as MODE. To make your programming file come through the scan chain, you have to add the device EPM7256B. The EPM device has to be the first on the list.
12. From the file menu you can now choose Create/update -> Create JAM, SVF or ISC file.
13. SSH to pc-rcu.fi.uib.no. Enter the directory where the .jam file has been saved (should be /your_working_directory/HLT-RORC/Quartus)
14. type jamplayer -p378 -aCONFIGURE top_module.jam.
In case you receive the following error message: "Error: can't open file "/heim/torheim/rorctest/HLT-RORC/Quartus/top_module.jam", ensure that you have set the correct user privileges for HLT-RORC directory including its files and folders. You can do this by typing chmod -R 666 HLT-RORC.
15. Reboot your system. The HLT-RORC should now be ready and running. On pc-rcu.fi.uib.no, BAR0 will probably be mapped to FB400000. This can be checked by typing /sbin/lspci -v from the command line.
Verifying the implementation with the Vanguard Logic Analyzer
1. Start the Analyzer (BusView.exe)
2. Choose File -> New -> Analyzer Setup
3. Add this event: PCI0 in transfer mode with address FD0xxxxx.
4. Add this trigger:
Samling in TRANSFER mode Store (ALL) If (PCI0) then Trigger at 50% of trace Endif
5. Cut and paste this text into an empty text file and save the file as testbench.scr:
f FB400000 FB400000 FD000000 f FB400004 FB400004 00000400 f FB400008 FB400008 FD000000 f FB40002C FB40002C FD000000 f FB400030 FB400030 FD000000 f FB400018 FB400018 00000011 f FB400020 FB400020 00000019 f FB400024 FB400024 00000001 f FB400024 FB400024 00000000 f FB400028 FB400028 AFFED00F
NB! This script assumes that the base address for BAR0 in the HLT-RORC is FB400000. It also assumes that the PCI base address for the Vanguard local target memory is FD000000.
6. Choose Exerciser -> Script -> Load and enter testbench.scr.
7. Choose Exerciser -> Target and enable the local target memory. Check that the Memory Window Address is consistent with the memory addresses in the script file.
8. Enter F9 to start sampling on the PCI bus. Then enter F10 to run the exerciser script. The exerciser script now runs the same scenario as in the VHDL testbench. If the HLT-RORC-4 design is working, the analyzer should be triggered by the HLT-RORC writing bursts of data words to the local memory.
9. Enter Alt-F9 to halt the analyser after the analyzer has been been triggered. Then choose Exerciser -> Local -> Display to examine the data written to local target memory by HLT-RORC.
Verifying the implementation with the software
NB! Step 1-2 can only be done by a user with root permission. The first steps should therefore be taken care of by the supervisor, so the students doing this exercise can jump directly to point 4.
1. To run the software, a kernel module called psi has to be inserted into the kernel. The PSI tar.gz file can be downloaded from http://www.kip.uni-heidelberg.de/ti/HLT/software/software.html. If you download PSI version 0.8.2 from august 2003, you will have to patch psi_mod.c to make it compile on newer kernels. A patchfile called psi_mod.patch is located in the HLT-RORC directory. Before compiling, remember to change the TOPDIR variable in the Makefile and remove -DWITHBIGPHYS if bigphys is not compiled into the kernel (and it probably isn't). Now you can install the module by entering directory psi-0.8.2\src\driver.linux and typing (in the following sequence):
make clean make module make install make dev (or typing manually mknod /dev/psi c 100 0) chmod 666 /dev/psi (to give normal users permission to access the device file)
The module can now be installed by typing insmod psi.o
(You will need root permissions to do this. If you want to use my precompiled binaries instead of compiling yourself, make sure to boot up the computer with the 2.4.20custum-bigphys kernel. You can check which kernel is running by typing 'uname -a'.)
Make sure that you are running with the same kernel when loading the module as when compiling the module, unless the modules wont work.
To compile the PSI API, go to directory psi-0.8.2\src\libpsi.linux and type make.
2. Enter directory HLT-RORC/src. If necessary, you will have to edit Makefile and Rules.make before compiling. Then run make all followed by make install, mknod /dev/irqsignal c 120 1 and chmod 666 /dev/irqsignal. Now you can insert the irqsignal module by typing insmod irqsignal major=120.
3. Enter directory HLT-RORC/example. Compile the included files by typing make generate_irq. Remember to change the PSIDIR variable in the Makefile before compiling.
4. Run the compiled program generate_irq. The program will set up the HLT-RORC card to start interrupt-driven DMA-transfers. A signal handler located in the generate_irq program will respond to the interrupts. The program can be terminated by pressing Ctrl-C.
5. To observe the transactions with the Vanguard Analyzer, use the same events and trigger conditions that were shown in the previous example.