Modelsim/Questa: Difference between revisions

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Mapping av alterabibliotek:
<pre>
vmap cycloneiii /prog/altera/vhdl_libs/cycloneiii
vmap lpm /prog/altera/vhdl_libs/lpm
vmap altera /prog/altera/vhdl_libs/altera
vmap altera_mf /prog/altera/vhdl_libs/altera_mf
</pre>
[[Simulering av VHDL]]
[[Simulering av VHDL]]


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== Referanselitteratur ==
== Referanselitteratur ==
[[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]]
[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]
 
[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]
 
[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]
 
[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)]
 
[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]
 
[http://m.eet.com/media/1151614/23798-46098.pdf 10 tips for generating reusable VHDL]


[[http://www.ashenden.com.au/ Ashenden Designs]]
[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide]


[[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]]
[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]


[[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)]]
[https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ]


[[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]]
[https://github.com/UVVM Bitvis UVVM på GitHub ]


[[Category:Mikroelektronikk]]
[[Category:Mikroelektronikk]]

Latest revision as of 21:13, 4 February 2021