FOCAL - Forward Calorimeter: Difference between revisions

Revision as of 13:23, 12 May 2011

This page should contain information about the Focal project, especially about the interfacing from the Mimosa chips to the readout electronics.

Overview

Simple description of the Alice Focal readout electronics.

Mimosa chips

preliminary user manual of Phase1
BSDL file of Phase1, which can be used for JTAG test, such as with an XJTAG module.
SVF file for pattern-only mode test of Phase1, Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.

Readout electronics

Adapterboard /Fanoutboard

The adapterboard and fan-out boards provide LVDS interfaces and JTAG interfaces between the Control and Read-out board and the Mimosa ASICs. Here is the schematics of the boards.

Spartan6 FPGA type: XC6SLX150-FGG676, speed-grade: 3
Examples of user constraint files for Spartan6 FPGAs: U1 , U2
EXamples of VHDL entity definations for Spartan6 FPGAs: U1 , U2

Control and Readout board

The idea is to use a Xilinx Virtex 6 development board as a first prototype. The board will run Petalinux, and some software to access the firmware registers. A software framework for the TPC detector is to be adapted for the use on the Virtex 6 board and Petalinux.

FPGA user constraint file for Virtex 6 development board

Firmware

The VHDL counterpart is to be found here: http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-fw/trunk/messagebuffer/

Software

The software driver for the message buffer system can be found here: http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-dcs/trunk/rculinux/dcscMsgBufferInterface/

Petalinux documentation: [1]

Download section

Shopping list

1x 2U 335mm Rack mount enclosure, Grey - 665-7712 - 556,29
1x RD-125A Switch Mode PSU, 5V/15A,12V/10A - 644-6941 - 662,16
3x DC/DC PoL,DOSA,2.4-5.5Vin,0.75-3.3Vo 6A - 150-758 - 116,16
1x 4.20mm,housing,MiniFit,receptacle,DR,6w, - 679-5773 - 2,064
http://www.samtec.com/search/vita57fmc.aspx
1x BULGIN - BZH01/Z0000/11 - INLET, IEC, SWITCHED, RED - F9997237 - 57,39
1x MH CONNECTORS - MH3101S-8821 - COUPLER, RJ45, SHIELDED - F1122292 - 92,11
12x TYCO ELECTRONICS / AMP - 5569262-1 - JACK, RJ45, MULTI PORT, 2X4 - F1162485 - 102,42
2x L-COM - ECF504B-UAB - Modular Coupler - F1702375 - 91,31
2x USB cables - F1076669 - F1308878

@@ Line 6: / Line 6: @@
 == Mimosa chips ==
 * [[Media:PH1-UserMan-20080916.pdf|preliminary user manual of Phase1]]
-* [[Media:mimosa.bsd.txt|BSDL file of Phase1]], which can be used for JTAG test, such as an XJTAG module.
+* [[Media:mimosa.bsd.txt|BSDL file of Phase1]], which can be used for JTAG test, such as with an XJTAG module.
 * [[Media:pattern_test.svf.txt|SVF file for pattern-only mode test of Phase1]], Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.