Difference between revisions of "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"

From ift
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[[File:Example.jpg|thumbnail]]Tested on Xilinx Vivado 2017.3.
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Tested on Xilinx Vivado 2017.3, using the Xilinx Digilent Zybo SoC.
 
 
  
 
Start ./vivado from installed directory.  
 
Start ./vivado from installed directory.  
 
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]
 
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]
Do not add any sources, but make sure that both Target and Simulator Language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.  
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Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub].
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Do not add any sources, but make sure that both target and simulator language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.  
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Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub]. Make sure that the option to copy the constraints file(s) into the project is marked.
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For the next step, the board files for the board we're using must have been installed. If this is not the case, follow [https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 this tutorial] to do so. [[File:new_project_default_part.png|thumbnail|center]]
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Choose the Zybo board, click next, and finish.

Revision as of 15:28, 28 November 2017

Tested on Xilinx Vivado 2017.3, using the Xilinx Digilent Zybo SoC.

Start ./vivado from installed directory.

Goto: File -> New Project -> Next. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next.

New project name.png

Do not add any sources, but make sure that both target and simulator language is set to the appropriate language you're using. In this project we will use VHDL. Click Next. Here you must provide a constraints file named "ZYBO_Master.xdc", available from GitHub. Make sure that the option to copy the constraints file(s) into the project is marked.

For the next step, the board files for the board we're using must have been installed. If this is not the case, follow this tutorial to do so.

New project default part.png

Choose the Zybo board, click next, and finish.