Difference between revisions of "Cadence Virtuoso overview"
From ift
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m (Some text to the different IC processes) |
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| − | = | + | = IC design flow using Cadence = |
| − | + | We have access to several silicon technologies from different foundries | |
| − | [[ IHP 130nm process ]] | + | * 130nm CMOS process from Taiwan Semiconductor Manufacturing: '''[[ TSMC 130nm process ]]''' |
| − | + | * 130nm SiGe process from Innovations for High Performance Microelectronics: '''[[ IHP 130nm process ]]''' | |
| − | [[ AMS 350nm process ]] | + | * 350nm CMOS process from Austria Mikro Systeme: '''[[ AMS 350nm process ]]''' |
= Simulation = | = Simulation = | ||
Revision as of 12:37, 18 October 2017
IC design flow using Cadence
We have access to several silicon technologies from different foundries
- 130nm CMOS process from Taiwan Semiconductor Manufacturing: TSMC 130nm process
- 130nm SiGe process from Innovations for High Performance Microelectronics: IHP 130nm process
- 350nm CMOS process from Austria Mikro Systeme: AMS 350nm process
Simulation
Layout
Helpful stuff
MikroserverSetup - setup for easy connection to the mikroservers and Cadence Virtuoso
Transistor operating point printer - Script to extract transistor operating point parameters after simulation.
ADEXL-butterfly-curves - Howto make DC butterfly curves easily.
