Cadence Virtuoso overview

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Revision as of 15:31, 15 September 2017 by Fli091 (talk | contribs) (Added Category:Integrated_Circuts)

Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)

TSMC 130nm process

IHP 130nm process

AMS 350nm process

Simulation

Virtuoso Testbench

Layout

Layout XL and IHP SG13S

Helpful stuff

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.

ADEXL-butterfly-curves - Howto make DC butterfly curves easily.