Difference between revisions of "Cadence Virtuoso overview"

From ift
Line 12: Line 12:
= Layout =
= Layout =
[[Get schematic ready for layout]]
[[Layout XL and IHP SG13S]]
[[Layout XL and IHP SG13S]]

Revision as of 10:15, 12 April 2016

Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)

TSMC 130nm process

IHP 130nm process

AMS 350nm process


Virtuoso Testbench


Layout XL and IHP SG13S

Helpful stuff

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.