Difference between revisions of "Cadence Virtuoso overview"

From ift
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=Analog IC design flow using Cadence from basics(Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)=
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=Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)=
  
 
[[ TSMC 130nm process ]]
 
[[ TSMC 130nm process ]]
 +
 +
[[ IHP 130nm process ]]
  
 
[[ AMS 350nm process ]]
 
[[ AMS 350nm process ]]
 
  
 
=Helpful stuff=
 
=Helpful stuff=

Revision as of 12:38, 25 August 2015

Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)

TSMC 130nm process

IHP 130nm process

AMS 350nm process

Helpful stuff

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.