Difference between revisions of "Bitvis UVVM VHDL Verification Component Framework"

From ift
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</pre>
 
</pre>
  
=== Introduction ===
+
== Introduction ==
  
 
Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for  
 
Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for  
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=== Let's create our own testbench for the IRQC ===
 
=== Let's create our own testbench for the IRQC ===
  
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. Open up bitvis_irqc/tb/irqc_tb.vhd and delete it! Let's start over....
+
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. Open up bitvis_irqc/tb/irqc_tb.vhd and delete the content! Let's start over....
  
 
<pre>
 
<pre>
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use work.irqc_pif_pkg.all;
 
use work.irqc_pif_pkg.all;
  
 +
-- Test case entity
 +
entity irqc_tb is
 +
end entity;
 +
 +
-- Test case architecture
 +
architecture func of irqc_tb is
 +
 +
  -- DSP interface and general control signals
 +
  signal clk          : std_logic  := '0';
 +
  signal arst          : std_logic  := '0';
 +
  -- CPU interface
 +
  signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
 +
 
 +
  -- Interrupt related signals
 +
  signal irq_source    : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');
 +
  signal irq2cpu      : std_logic := '0';
 +
  signal irq2cpu_ack  : std_logic := '0';
 +
 +
 +
  signal clock_ena  : boolean := false;
 +
 +
  constant C_CLK_PERIOD : time := 10 ns;
 +
 +
 +
  procedure clock_gen(
 +
    signal  clock_signal  : inout std_logic;
 +
    signal  clock_ena    : in    boolean;
 +
    constant clock_period  : in    time
 +
  ) is
 +
    variable v_first_half_clk_period : time := C_CLK_PERIOD / 2;
 +
  begin
 +
    loop
 +
      if not clock_ena then
 +
        wait until clock_ena;
 +
      end if;
 +
      wait for v_first_half_clk_period;
 +
      clock_signal <= not clock_signal;
 +
      wait for (clock_period - v_first_half_clk_period);
 +
      clock_signal <= not clock_signal;
 +
    end loop;
 +
  end;
 +
 +
  subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);
 +
 +
 
 +
begin
 +
-- HERE YOU WILL PUT THE REST OF THE CODE!
 +
 +
end func;
 
</pre>
 
</pre>
  
  
  
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. We can start trying out the example testbench before continuing. Open up Questa/Modelsim.
+
==Open up Questa/Modelsim==
 
Change directory to the script folder (obviously change to your folder.....):
 
Change directory to the script folder (obviously change to your folder.....):
 
<pre>
 
<pre>

Revision as of 15:09, 26 January 2016

-- Copyright (c) 2016 by Bitvis AS.  All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, 
-- contact Bitvis AS <support@bitvis.no>.
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM.
--========================================================================================================================

Introduction

Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the Bitvis web page.

What's in the folders?

1.png

The download includes severals folders:

  • bitvis_irqc - example VHDL design + testbench
  • bitvis_uart - example VHDL design + testbench
  • bitvis_vip_sbi - Verification IP(VIP) for simple bus interface(SBI)
  • bitvis_vip_uart - VIP for UART TX and RX
  • uvvm_util - UVVM utility library - sufficient for simple testbenches
  • uvvm_vvc_framework - Framework for more advanced tutorials

Let's create our own testbench for the IRQC

Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. Open up bitvis_irqc/tb/irqc_tb.vhd and delete the content! Let's start over....

-- Add the standard libraries
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library STD;
use std.env.all;

--Also add the Bitvis UVVM Utility Library
library uvvm_util;
context uvvm_util.uvvm_util_context;

--And the Verification IP for the simple bus interface
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;

--And the design's package file
use work.irqc_pif_pkg.all;

-- Test case entity
entity irqc_tb is
end entity;

-- Test case architecture
architecture func of irqc_tb is

  -- DSP interface and general control signals
  signal clk           : std_logic  := '0';
  signal arst          : std_logic  := '0';
  -- CPU interface
  signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
  
  -- Interrupt related signals
  signal irq_source    : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');
  signal irq2cpu       : std_logic := '0';
  signal irq2cpu_ack   : std_logic := '0';


  signal clock_ena  : boolean := false;

  constant C_CLK_PERIOD : time := 10 ns;


  procedure clock_gen(
    signal   clock_signal  : inout std_logic;
    signal   clock_ena     : in    boolean;
    constant clock_period  : in    time
  ) is
    variable v_first_half_clk_period : time := C_CLK_PERIOD / 2;
  begin
    loop
      if not clock_ena then
        wait until clock_ena;
      end if;
      wait for v_first_half_clk_period;
      clock_signal <= not clock_signal;
      wait for (clock_period - v_first_half_clk_period);
      clock_signal <= not clock_signal;
    end loop;
  end;

  subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);

  
begin
-- HERE YOU WILL PUT THE REST OF THE CODE!

end func;


Open up Questa/Modelsim

Change directory to the script folder (obviously change to your folder.....):

cd ~/phys321/bitviswiki/bitvis_irqc/script
do compile_and_sim_all.do