Difference between revisions of "Bitvis UVVM VHDL Verification Component Framework"

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=== What's included? ===
=== What's included? ===
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Revision as of 14:11, 26 January 2016


Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the Bitvis web page.

What's included?