Bitvis UVVM VHDL Verification Component Framework: Difference between revisions
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Revision as of 13:03, 26 January 2016
Introduction
Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the Bitvis web page.
