http://ift.wiki.uib.no/api.php?action=feedcontributions&user=Put009&feedformat=atomift - User contributions [en]2024-03-29T02:23:45ZUser contributionsMediaWiki 1.39.6http://ift.wiki.uib.no/index.php?title=TSMC_130nm_process&diff=2710TSMC 130nm process2018-11-06T09:50:53Z<p>Put009: Added if IHP are used, use SG13_dev technology</p>
<hr />
<div>=Cadence design with TSMC 130nm process=<br />
This tutorial will start from very basics in analog IC design then take you through the whole analog IC design process.<br />
<br />
Here is the outline of the analog IC design flow:<br />
# Schematic capture (Cadence tool)<br />
# Netlist extraction from schematic<br />
# Simulating using ELDO simulator and viewing results with EZWAVE (ELDO is a Mentor Graphic's tool for netlist level simulations)<br />
# Layout using Cadence<br />
# Signoff layout (DRC, LVS and parasitic extraction) using Calibre (Calibre is a Mentor Graphic's tool)<br />
<br />
==Setup of Cadence==<br />
<br />
To start virtuoso one must first connect to mikroserver3<br />
ssh -X mikroserver3<br />
<br />
<br />
'''First''' time you should add the following line to your cds.lib-file by running this command: <br />
mkdir ~/tsmc<br />
echo "DEFINE tsmc13rf /eda/design_kits/tsmc_013/tsmc13rf" > ~/tsmc/cds.lib<br />
<br />
Then ('''each time''') run these commands to set up Cadence<br />
source /eda/cadence/2016-17/scripts/analog_flow.sh<br />
source /eda/cadence/eda_general_init.sh<br />
<br />
Virtuoso Mixed Signal Design Environment is started by issuing this command:<br />
virtuoso &<br />
<br />
=== Troubleshooting ===<br />
* Make sure you source the script from the correct year. I.e 2016-17 and not 2015-16<br />
* Make sure you are connected the the right mikroserver<br />
* Make sure you run virtuoso from the same folder as your 'cds.lib'-folder ('~/tsmc/')<br />
<br />
== Getting started ==<br />
<br />
In the log window, choose "File > New > Library".<br />
<br />
In the "New Library" dialog box, you must give the library a name (for example TORLIB, as I did). You must also specify a technology file. Here you choose "Attach to an existing technology library". Then click the OK button. When asked for technology, choose "tsmc13rf". If you are using IHP instead, choose "SG13_dev".<br />
<br />
After successfully creating the new library, it is time to create your first design. In the log window, choose "File > New > Cellview". In the "Create New File" dialog box, you must give the design a name. You must also specify which library the design belongs to, and here you specify the library that you have just created. Choose to open the cell with "Schematics XL" and add a check-mark to always use this application if it is not checked.<br />
<br />
Now click OK, and the Virtuoso Schematic Editor should pop up. We will now draw a simple inverter design, as shown in the picture:<br />
<br />
[[File:virtuoso_schematic_editor.png|400px]]<br />
<br />
==Entering the design==<br />
To create the inverter design, do the following:<br />
<br />
# Press 'i' or click on the "Instance" icon to invoke the transistors. The "Add Instance" dialog box will now pop up. In the "Library" field, click "Browse" to open the "Library Browser". In the library browser, choose "tsmc13rf" as library, "nmos3v" (for n-type transistor) or "pmos3v" (for p-type transistor) as cell and "spectre" as view. The cell is placed in the schematic by moving the cursor to the desired location and clicking the left mouse button.<br />
# To insert the voltage sources, pick the "vdc" cell from the "analogLib" library. Add one connected to vdd and gnd and one connected to the input.<br />
# To insert the ground and vdd nets, pick the "vdd" and "gnd" cells from the "analogLib" library. Here the view name should be "symbol", not "spectreS" (in fact, "symbol" is the only available option).<br />
# To connect the symbols, press 'w' or click the "Wire (narrow)" icon. Then use the left mouse button to click the nodes togeter, two by two.<br />
# To remove an instance or a wire, left click at the instance or wire that you want to remove, then press the "Delete" button on the keyboard.<br />
# To insert a pin, press 'p'. Choose a name for the pin in the dialog that occurs and click on the schematic to place it. Create one input and one output.<br />
# To change the properties of the icons, press 'q' or click at the "Properties" icon. Then click at the instances or nets that you want to modify. For the vdc source connected between vdd and gnd, set the "DC voltage" property to 3.3.<br />
# To check and save the schematic, press 'x' or click the "Check and save" icon. <br />
# If there are any errors or warnings, press ok and press 'g' or "Check->Find Marker" to view the errors. Make sure you have no errors or warnings before continuing. <br />
<br />
==Simulating the design==<br />
<br />
# Open "Launch > ADE GXL" and press create new view. The "Virtuoso Analog Environment" should now come up.<br />
# Choose "Create > Test..." select the cell to simulate.<br />
# Choose "Outputs > To be plotted > Select on Schematic". Click at the "in" node connected to the inverter input and the "out" node connected to the output.<br />
# Choose "Analyses > Choose". We will now run a dc analysis to obtain the DC transfer characteristics of the inverter. Choose "Component parameter" as your sweep variable. Then click at "Select component". In the schematic, click at the input "vdc" instance. In the "Select Component Parameter" dialog box, choose dc as your sweep parameter. The sweep range should go from 0 to 3.3.<br />
<br />
[[File:select_comp_parameter.png|300px]]<br />
<br />
The analog environment should now look like this:<br />
<br />
[[File:analog_env_2.png|500px]]<br />
<br />
Switch to the "adexl" tab and choose the green run button. When the run is completed press the graph button beside the box that says "Replace". The outputs should look like this:<br />
[[File:plot_output_dc.png|600px]]<br />
<br />
To save your simulation settings, choose "Session > Save state" in the test editor windoe to save your state information under whatever file name you want. In a later session, you can reload your saved states using "Session > Load state".<br />
<br />
==Generating a Symbol==<br />
Finally, we want to generate a symbol for our inverter. This symbol is needed if we want to use our inverter design inside another design (hierarchical design methodology). <br />
<br />
Select the schematic tab and choose "Create -> Create Cellview -> From Cellview". <br />
<br />
Press OK in the dialog that occurs.<br />
<br />
The pins should already be connected to the right positions in the symbol generator, so press OK here also and ths symbol editor will occur.<br />
<br />
Press the red X and delete the pre-created green square. Use the line tool and the circle tool to create the inverter symbol<br />
<br />
[[File:symbol.png|400px]]<br />
<br />
Save it by clicking the "Save and check" symbol or pressing 'shift+X'.<br />
<br />
[[Category:Mikroelektronikk]] [[Category:Integrated_Circuts]]</div>Put009http://ift.wiki.uib.no/index.php?title=Layout_XL_and_IHP_SG13S&diff=2701Layout XL and IHP SG13S2018-05-04T15:47:57Z<p>Put009: Added Parasitic extraction QRC and Post Layout Simulation</p>
<hr />
<div>= Before starting layout =<br />
<br />
Read the Design Kit User Guide. Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.<br />
The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/doc/pdf" on the microserver.<br />
<br />
[[File:Documentation.png|200px]]<br />
<br />
If your laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed"). <br />
<br />
= Layout XL =<br />
<br />
From the schematic click Launch -> Layout XL to open the layout environment.<br />
<br />
[[File:layout.png|200px]] [[File:layout2.png|200px]]<br />
<br />
Layout XL opens with a new black empty canvas. The schematic window also opens. This is very useful as when we add our devices in the layout we can see which device they represent in the schematic as they get highlighted.<br />
<br />
Before anything you must define some options to avoid a lot of DRC-errors down the line. In the Layout Rules-document we read what our drawing-grid restrictions are (bottom of page 10). In Layout XL press E to open the Display Options-window. Remember that all size-values are in micrometers. Set the X and Y Snap Spacing to reflect the grid rules. Now press Shift-E to open the Layout Editor Options. Set gravity on(you can turn this off later with the g-key if you dont like it), and aperture around 0.1. This defines the the distance before snapping to another object etc.<br />
<br />
[[File:grid.png|200px]] [[File:gravity.png|200px]]<br />
<br />
= Generate from source =<br />
<br />
IHP has already defined transistors, pins, etc. for different sized, so it is not needed to draw these from scratch. You should, however, dissect them to understand how they work. To place all the devices from the schematic press Connectivity -> Generate -> All From Source. In this window we define which of our devices we want to place, the I/O pins, PR boundary (the area which our cell must be within) and floorplan settings (if needed). For our cell we need to change the IO-pins. We want the gnd and bit-lines to be vertical, and vdd and word-lines to be horizontal. This means that they will intersect each other and must be in different layers. We also want two gnd-pins which also can be defined here. Remember to uncheck Create under the sub!-pin since this is not needed. <br />
<br />
Change the Label options to a smaller font size (about 0.1 is ok). Click OK to see the results.<br />
<br />
[[File:result.png|600px]]<br />
<br />
The purple box is the PR boundary in which are layout must be contained. Notice how the ntap1 is highlighted in the schematic when clicked in the layout window.<br />
<br />
= Pin Placement =<br />
<br />
Press Place -> Pin Placement. This opens a windows that lets us define the position of our pins. This is very helpful to line up our design. Remember that the positions may be tweaked later.<br />
<br />
[[File:pinplacement.png|400px]]<br />
<br />
= Placing devices =<br />
<br />
If you are extremely lazy you can autoplace the components with Place -> Custom Digital -> Placer. This, however, will probably not give you the desired result. To help you place the the devices correctly it is helpful to see which devices that connect to each other and how. This is accomplished with Connectivity -> Nets -> Show/Hide All Incomplete Nets. This will give you a all the nets that are uncompleted and can be very daunting. However, you can use Ctrl++ (that is Ctrl and +-key ) to turn on or off the nets for the selected device. <br />
<br />
F4 switches between Full and Partial Select. Partial Select means that we are able to select individual pieces of a device, e.g. if we want to stretch a part.<br />
<br />
[[File:partial.png|50px]] [[File:partial2.png|50px]]<br />
<br />
== DRD ==<br />
[[File:DRDbuttons.png|50px]]<br />
<br />
DRD stands for Dynamic Design Rule Checking and are helpful while laying out your design. DRD Enforce On prevents you from doing anything that breaks the rules, and DRD Notify tells you if what you are doing is illegal. Image below shows example of DRD Notify.<br />
<br />
[[File:DRD.png|200px]]<br />
<br />
== Drawing ==<br />
<br />
To draw rectangles (e.g. NWell) choose the wanted layer on the left side then press R. To create a connection between to nodes you can either create a wire (Ctrl+W) or a path (P). A wire automatically helps with choosing layer, and may also be used to create vias to another layer by left-clicking.<br />
<br />
A complete layout could look something like this:<br />
<br />
[[File:sram.png|600px]]<br />
<br />
= DRC =<br />
<br />
Run DRC by pressing Assura -> Run DRC. Make sure technology is SG13_dev and the Rule Set is default. Read about the different switches in the user guide (e.g. antenna-rules etc). If everything is ok this message should appear:<br />
<br />
[[File:drcok.png|200px]]<br />
<br />
The DRC should also be run for Density. See IHP user guide for how to produce dummy metal to fill the design.<br />
<br />
= LVS =<br />
<br />
This is covered in chapter 12 of the user guide.<br />
<br />
Run LVS by pressing Assura -> Run LVS. This will give you a match if the schematic and the layout match each other, or you will get some errors.<br />
<br />
[[File:LVS_summary.png|200px]]<br />
<br />
= Parasitic extraction QRC =<br />
<br />
This is covered in chapter 14 of the user guide. Before you run the QRC, the LVS has to match.<br />
<br />
To do an extraction of your circuit click Assura -> Run Quantus QRC. In "Setup Dir" make sure the path is set to "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/Assura_SG13/qrc", where the technology files for the qrc run is. Set the "Parasitic Res Component" to "presistor ivpcell SG13_dev" and the "Parasitic Cap Component" to "pcapacitor ivpcell SG13_dev". The run the QRC.<br />
<br />
[[File:ASSURA_QRC.png|400px]]<br />
<br />
This should give you an extracted design called "av_extracted" in the cell of the library. This can be checked and viewed from the library manager. In this picture the extracted cell is a SRAM with bitline conditioning and a write driver.<br />
<br />
[[File:Extracted_layout_SRAM_with_bt_wd.png|400px]]<br />
<br />
= Post layout simulation =<br />
<br />
In the library manager make an copy of the SRAM cell, to use as a test bench cell. Click file -> new -> Cell View and make an config file in your new test bench cell. Use "config" as the type, and click "ok". In the new window click on the "Use template" and select "AMS", and click "ok". Then edit the view list and add "av_extracted" with the add box. Clicking ok will then bring you to the hierarchy editor.<br />
<br />
Then you need a test bench schematic. In your copied schematic you will have the whole SRAM or different symbols making up the SRAM, but for the simulation there should only be a symbol that matches the extracted layout. So go back to the schematic in the SRAM cell and make one symbol out of it. Put this symbol into the test bench schematic, and add the pins that are needed.<br />
<br />
Go back to the hierarchy editor and change the View to your test bench schematic and update the hierarchy. Then right click on the "view found" for the SRAM from the SRAM cell, and select the av_extracted.<br />
<br />
[[File:Hierarchy_editor.png|400px]]<br />
<br />
Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.<br />
<br />
[[Category:Mikroelektronikk]]</div>Put009http://ift.wiki.uib.no/index.php?title=File:Hierarchy_editor.png&diff=2700File:Hierarchy editor.png2018-05-04T15:28:55Z<p>Put009: </p>
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<div></div>Put009http://ift.wiki.uib.no/index.php?title=File:LVS_summary.png&diff=2699File:LVS summary.png2018-05-04T15:00:27Z<p>Put009: </p>
<hr />
<div></div>Put009http://ift.wiki.uib.no/index.php?title=File:Extracted_layout_SRAM_with_bt_wd.png&diff=2698File:Extracted layout SRAM with bt wd.png2018-05-04T11:43:10Z<p>Put009: </p>
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<div></div>Put009http://ift.wiki.uib.no/index.php?title=File:ASSURA_QRC.png&diff=2697File:ASSURA QRC.png2018-05-03T08:52:49Z<p>Put009: </p>
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<div></div>Put009http://ift.wiki.uib.no/index.php?title=MikroserverSetup&diff=2696MikroserverSetup2018-04-21T17:17:17Z<p>Put009: Added command for copying folders</p>
<hr />
<div>= Set-up of connection to mikroservers and cadence virtuoso = <br />
<br />
This set-up will allow you to connect to the mikroservers and/or start Cadence virtuoso with one command without typing any password or host-names.<br />
<br />
<br />
'''''NB: This setup is for TSMC, but the commands can be tweaked to be used with IHP or AMS too.'''''<br />
<br />
<br />
The three mikroservers are :<br />
* mikroserver1.klientdrift.uib.no<br />
* mikroserver2.klientdrift.uib.no<br />
* mikroserver3.klientdrift.uib.no<br />
<br />
<br />
== SSH key == <br />
* Generate an ssh-key<br />
ssh-keygen -f ~/.ssh/id.rsa -t rsa -N '' <br />
<br />
* Copy the key with your identity to your chosen mikroserver (mikroserver3 is chosen in this example). NB: Replace USERNAME with your user name<br />
<br />
ssh-copy-id USERNAME@mikroserver3.klientdrift.uib.no<br />
<br />
<br />
== Connection aliases ==<br />
<br />
For ease of use set up aliases for the connections in your terminal. Open .bashrc in a text editor (vim / nano) and type in this <br />
<br />
alias mikroserver1='ssh -X USERNAME@mikroserver1.klientdrift.uib.no'<br />
alias mikroserver2='ssh -X USERNAME@mikroserver2.klientdrift.uib.no'<br />
alias mikroserver3='ssh -X USERNAME@mikroserver3.klientdrift.uib.no'<br />
<br />
Also create another alias for your favourite mikroserver <br />
echo "alias mikroserver='ssh -X USERNAME@mikroserver3.klientdrift.uib.no'" >> ~/.bashrc<br />
<br />
<br />
== Automatic sourcing ==<br />
<br />
Source scripts inside .bashrc. This will make sure the scripts are loaded every time you log in, so you don't have to do it manually<br />
# TSMC setup<br />
echo "source /eda/cadence/2016-17/scripts/analog_flow.sh" >> ~/.bashrc<br />
echo "source /eda/cadence/eda_general_init.sh" >> ~/.bashrc<br />
# IHP setup<br />
echo "source ~/ihp/cds/sh.cadence" >> ~/.bashrc<br />
<br />
== Commands to run virtuoso remotely == <br />
Then finally on the computers in the lab (NOT connected to the mikroservers)<br />
echo "alias virtuoso_tsmc="ssh -X USERNAME@mikroserver3.klientdrift.uib.no 'cd tsmc;virtuoso &'"" >> ~/.bashrc<br />
echo "alias virtuoso_ihp="ssh -X USERNAME@mikroserver3.klientdrift.uib.no 'cd ihp/cds;virtuoso &'"" >> ~/.bashrc<br />
<br />
The next time you open your terminal on your computer you can type <br />
virtuoso_tsmc<br />
to start Cadence Virtuoso, or <br />
mikroserver<br />
to connect to mikroserver3 without any hassle!<br />
<br />
== Add mikroserver as a folder on your pc ==<br />
<br />
Open up your home folder in linux and in the bottom left corner click "Connect to Server" as shown in this picture:<br />
[[File:ConnectToServer.png|thumbnail]]<br />
<br />
as server address type:<br />
sftp://mikroserver3.ift.uib.no/home/USERNAME<br />
to add your homefolder on mikroserver as a folder on your local PC for easy access to your files (for example the [[Transistor_operating_point_printer]])<br />
To store this connection, right click the "mikroserver3"-folder and click "Add Bookmark". The next time you just click the bookmark to open it.<br />
<br />
=== Alternative way using scp/secure copy===<br />
If for some reason the above doesn’t work you can try this:<br />
* connect to your mikroserver (ssh mikroserver3)<br />
* locate the file you want to copy. i.e /home/fredrik/picture.jpg<br />
* type this command<br />
scp picture.jpg USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
* this will copy the file to your home folder on any UiB machine<br />
* To copy a folder<br />
scp -r NameOfFolder USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
<br />
== Troubleshooting == <br />
* Make sure you copy your ID (ssh-copy-id) to the correct mikroserver<br />
* Make sure you have restarted your terminal (or source ~/.bashrc) if the commands doesn't work<br />
* You have to be either connected to the UiB VPN or run the commands via the computers in the lab to be able to connect to microserver<br />
* If you are using another shell like zsh or csh the aliases has to be in ~/.zshrc or ~/.cshrc instead of ~/.bashrc<br />
* Make sure you have replaced all the instances of USERNAME with your usename, i.e "fli091"<br />
<br />
<br />
[[Category:Mikroelektronikk]]</div>Put009http://ift.wiki.uib.no/index.php?title=Cadence_Testbench&diff=2695Cadence Testbench2018-04-21T17:01:31Z<p>Put009: Added simulation procedure</p>
<hr />
<div>= Simulate with corner cases =<br />
<br />
To simulate with the corner cases in the fabrication process you have to add the corner files provided in the design kit.<br />
<br />
[[File:Selection_001.png|200px]]<br />
<br />
Choose "Click to add corner"<br />
<br />
"Click to add" the model files you need.<br />
<br />
Ex. The corner files for the MOS transistor in IHP130nm process is located in<br />
$IHP_TECH/tech/SG13_MOS/library/spectre/cornerMOSlv_psp.scs<br />
<br />
After adding the model files needed proceed by adding multiple corners:<br />
<br />
[[File:corner.png|400px]]<br />
<br />
The model files contains sections with the different corners. Choose sections and make sure you enable the section "tick box" and name the corner with a corresponding name:<br />
<br />
[[File:sections.png|400px]]<br />
<br />
The corners setup also makes it possible to simulate for different temperatures or design variables like VDD and transistor length.<br />
Ex. test for three different temperatures with comma as separation: -20,30,80<br />
<br />
[[File:complete.png|400px]]<br />
<br />
<br />
To the do the simulation take a look at the "Data View" tab again. Make sure you have selected the corners, the desired test and global variables, and that they have the correct value.<br />
<br />
Then at the drop down menu in the toolbar, where stand "Single Run, Sweeps and Corners" click the light green play button. This will run the selected test, with your parameter values and selected corners.<br />
<br />
Wait for the simulation to complete, and then you can plot different corners, or use the "Plot All" button to get all corners plotted.<br />
<br />
[[Category:Mikroelektronikk]]</div>Put009http://ift.wiki.uib.no/index.php?title=TSMC_130nm_process&diff=2694TSMC 130nm process2018-04-11T13:33:24Z<p>Put009: </p>
<hr />
<div>=Cadence design with TSMC 130nm process=<br />
This tutorial will start from very basics in analog IC design then take you through the whole analog IC design process.<br />
<br />
Here is the outline of the analog IC design flow:<br />
# Schematic capture (Cadence tool)<br />
# Netlist extraction from schematic<br />
# Simulating using ELDO simulator and viewing results with EZWAVE (ELDO is a Mentor Graphic's tool for netlist level simulations)<br />
# Layout using Cadence<br />
# Signoff layout (DRC, LVS and parasitic extraction) using Calibre (Calibre is a Mentor Graphic's tool)<br />
<br />
==Setup of Cadence==<br />
<br />
To start virtuoso one must first connect to mikroserver3<br />
ssh -X mikroserver3<br />
<br />
<br />
'''First''' time you should add the following line to your cds.lib-file by running this command: <br />
mkdir ~/tsmc<br />
echo "DEFINE tsmc13rf /eda/design_kits/tsmc_013/tsmc13rf" > ~/tsmc/cds.lib<br />
<br />
Then ('''each time''') run these commands to set up Cadence<br />
source /eda/cadence/2016-17/scripts/analog_flow.sh<br />
source /eda/cadence/eda_general_init.sh<br />
<br />
Virtuoso Mixed Signal Design Environment is started by issuing this command:<br />
virtuoso &<br />
<br />
=== Troubleshooting ===<br />
* Make sure you source the script from the correct year. I.e 2016-17 and not 2015-16<br />
* Make sure you are connected the the right mikroserver<br />
* Make sure you run virtuoso from the same folder as your 'cds.lib'-folder ('~/tsmc/')<br />
<br />
== Getting started ==<br />
<br />
In the log window, choose "File > New > Library".<br />
<br />
In the "New Library" dialog box, you must give the library a name (for example TORLIB, as I did). You must also specify a technology file. Here you choose "Attach to an existing technology library". Then click the OK button. When asked for technology, choose "tsmc13rf".<br />
<br />
After successfully creating the new library, it is time to create your first design. In the log window, choose "File > New > Cellview". In the "Create New File" dialog box, you must give the design a name. You must also specify which library the design belongs to, and here you specify the library that you have just created. Choose to open the cell with "Schematics XL" and add a check-mark to always use this application if it is not checked.<br />
<br />
Now click OK, and the Virtuoso Schematic Editor should pop up. We will now draw a simple inverter design, as shown in the picture:<br />
<br />
[[File:virtuoso_schematic_editor.png|400px]]<br />
<br />
==Entering the design==<br />
To create the inverter design, do the following:<br />
<br />
# Press 'i' or click on the "Instance" icon to invoke the transistors. The "Add Instance" dialog box will now pop up. In the "Library" field, click "Browse" to open the "Library Browser". In the library browser, choose "tsmc13rf" as library, "nmos3v" (for n-type transistor) or "pmos3v" (for p-type transistor) as cell and "spectre" as view. The cell is placed in the schematic by moving the cursor to the desired location and clicking the left mouse button.<br />
# To insert the voltage sources, pick the "vdc" cell from the "analogLib" library. Add one connected to vdd and gnd and one connected to the input.<br />
# To insert the ground and vdd nets, pick the "vdd" and "gnd" cells from the "analogLib" library. Here the view name should be "symbol", not "spectreS" (in fact, "symbol" is the only available option).<br />
# To connect the symbols, press 'w' or click the "Wire (narrow)" icon. Then use the left mouse button to click the nodes togeter, two by two.<br />
# To remove an instance or a wire, left click at the instance or wire that you want to remove, then press the "Delete" button on the keyboard.<br />
# To insert a pin, press 'p'. Choose a name for the pin in the dialog that occurs and click on the schematic to place it. Create one input and one output.<br />
# To change the properties of the icons, press 'q' or click at the "Properties" icon. Then click at the instances or nets that you want to modify. For the vdc source connected between vdd and gnd, set the "DC voltage" property to 3.3.<br />
# To check and save the schematic, press 'x' or click the "Check and save" icon. <br />
# If there are any errors or warnings, press ok and press 'g' or "Check->Find Marker" to view the errors. Make sure you have no errors or warnings before continuing. <br />
<br />
==Simulating the design==<br />
<br />
# Open "Launch > ADE GXL" and press create new view. The "Virtuoso Analog Environment" should now come up.<br />
# Choose "Create > Test..." select the cell to simulate.<br />
# Choose "Outputs > To be plotted > Select on Schematic". Click at the "in" node connected to the inverter input and the "out" node connected to the output.<br />
# Choose "Analyses > Choose". We will now run a dc analysis to obtain the DC transfer characteristics of the inverter. Choose "Component parameter" as your sweep variable. Then click at "Select component". In the schematic, click at the input "vdc" instance. In the "Select Component Parameter" dialog box, choose dc as your sweep parameter. The sweep range should go from 0 to 3.3.<br />
<br />
[[File:select_comp_parameter.png|300px]]<br />
<br />
The analog environment should now look like this:<br />
<br />
[[File:analog_env_2.png|500px]]<br />
<br />
Switch to the "adexl" tab and choose the green run button. When the run is completed press the graph button beside the box that says "Replace". The outputs should look like this:<br />
[[File:plot_output_dc.png|600px]]<br />
<br />
To save your simulation settings, choose "Session > Save state" in the test editor windoe to save your state information under whatever file name you want. In a later session, you can reload your saved states using "Session > Load state".<br />
<br />
==Generating a Symbol==<br />
Finally, we want to generate a symbol for our inverter. This symbol is needed if we want to use our inverter design inside another design (hierarchical design methodology). <br />
<br />
Select the schematic tab and choose "Create -> Create Cellview -> From Cellview". <br />
<br />
Press OK in the dialog that occurs.<br />
<br />
The pins should already be connected to the right positions in the symbol generator, so press OK here also and ths symbol editor will occur.<br />
<br />
Press the red X and delete the pre-created green square. Use the line tool and the circle tool to create the inverter symbol<br />
<br />
[[File:symbol.png|400px]]<br />
<br />
Save it by clicking the "Save and check" symbol or pressing 'shift+X'.<br />
<br />
[[Category:Mikroelektronikk]] [[Category:Integrated_Circuts]]</div>Put009http://ift.wiki.uib.no/index.php?title=TSMC_130nm_process&diff=2693TSMC 130nm process2018-04-11T11:46:17Z<p>Put009: Moved launch ade gxl from entering to simulation</p>
<hr />
<div>=Cadence design with TSMC 130nm process=<br />
This tutorial will start from very basics in analog IC design then take you through the whole analog IC design process.<br />
<br />
Here is the outline of the analog IC design flow:<br />
# Schematic capture (Cadence tool)<br />
# Netlist extraction from schematic<br />
# Simulating using ELDO simulator and viewing results with EZWAVE (ELDO is a Mentor Graphic's tool for netlist level simulations)<br />
# Layout using Cadence<br />
# Signoff layout (DRC, LVS and parasitic extraction) using Calibre (Calibre is a Mentor Graphic's tool)<br />
<br />
==Setup of Cadence==<br />
<br />
To start virtuoso one must first connect to mikroserver3<br />
ssh -X mikroserver3<br />
<br />
<br />
'''First''' time you should add the following line to your cds.lib-file by running this command: <br />
mkdir ~/tsmc<br />
echo "DEFINE tsmc13rf /eda/design_kits/tsmc_013/tsmc13rf" > ~/tsmc/cds.lib<br />
<br />
Then ('''each time''') run these commands to set up Cadence<br />
source /eda/cadence/2016-17/scripts/analog_flow.sh<br />
source /eda/cadence/eda_general_init.sh<br />
<br />
Virtuoso Mixed Signal Design Environment is started by issuing this command:<br />
virtuoso &<br />
<br />
=== Troubleshooting ===<br />
* Make sure you source the script from the correct year. I.e 2016-17 and not 2015-16<br />
* Make sure you are connected the the right mikroserver<br />
* Make sure you run virtuoso from the same folder as your 'cds.lib'-folder ('~/tsmc/')<br />
<br />
== Getting started ==<br />
<br />
In the log window, choose "File > New > Library".<br />
<br />
In the "New Library" dialog box, you must give the library a name (for example TORLIB, as I did). You must also specify a technology file. Here you choose "Attach to an existing technology library". Then click the OK button. When asked for technology, choose "tsmc13rf".<br />
<br />
After successfully creating the new library, it is time to create your first design. In the log window, choose "File > New > Cellview". In the "Create New File" dialog box, you must give the design a name. You must also specify which library the design belongs to, and here you specify the library that you have just created. Choose to open the cell with "Schematics XL" and add a check-mark to always use this application if it is not checked.<br />
<br />
Now click OK, and the Virtuoso Schematic Editor should pop up. We will now draw a simple inverter design, as shown in the picture:<br />
<br />
[[File:virtuoso_schematic_editor.png|400px]]<br />
<br />
==Entering the design==<br />
To create the inverter design, do the following:<br />
<br />
# Press 'i' or click on the "Instance" icon to invoke the transistors. The "Add Instance" dialog box will now pop up. In the "Library" field, click "Browse" to open the "Library Browser". In the library browser, choose "tsmc13rf" as library, "nmos3v" (for n-type transistor) or "pmos3v" (for p-type transistor) as cell and "spectre" as view. The cell is placed in the schematic by moving the cursor to the desired location and clicking the left mouse button.<br />
# To insert the voltage sources, pick the "vdc" cell from the "analogLib" library. Add one connected to vdd and gnd and one connected to the input.<br />
# To insert the ground and vdd nets, pick the "vdd" and "gnd" cells from the "analogLib" library. Here the view name should be "symbol", not "spectreS" (in fact, "symbol" is the only available option).<br />
# To connect the symbols, press 'w' or click the "Wire (narrow)" icon. Then use the left mouse button to click the nodes togeter, two by two.<br />
# To remove an instance or a wire, left click at the instance or wire that you want to remove, then press the "Delete" button on the keyboard.<br />
# To insert a pin, press 'p'. Choose a name for the pin in the dialog that occurs and click on the schematic to place it. Create one input and one output.<br />
# To change the properties of the icons, press 'q' or click at the "Properties" icon. Then click at the instances or nets that you want to modify. For the vdc source connected between vdd and gnd, set the "DC voltage" property to 3.3.<br />
# To check and save the schematic, press 'x' or click the "Check and save" icon. <br />
# If there are any errors or warnings, press ok and press 'g' or "Check->Find Marker" to view the errors. Make sure you have no errors or warnings before continuing. <br />
<br />
==Simulating the design==<br />
<br />
# Open "Launch > ADE GXL" and press create new view. The "Virtuoso Analog Environment" should now come up.<br />
# Choose "Create > Test..." select the cell to simulate.<br />
# Choose "Outputs > To be plotted > Select on Schematic". Click at the "in" node connected to the inverter input and the "out" node connected to the output.<br />
# Choose "Analyses > Choose". We will now run a dc analysis to obtain the DC transfer characteristics of the inverter. Choose "Component parameter" as your sweep variable. Then click at "Select component". In the schematic, click at the input "vdc" instance. In the "Select Component Parameter" dialog box, choose dc as your sweep parameter. The sweep range should go from 0 to 3.3.<br />
[[File:select_comp_parameter.png|300px]]<br />
The analog environment should now look like this:<br />
[[File:analog_env_2.png|500px]]<br />
# Switch to the "adexl" tab and choose the green run button. When the run is completed press the graph button beside the box that says "Replace". The outputs should look like this:<br />
[[File:plot_output_dc.png|600px]]<br />
<br />
To save your simulation settings, choose "Session > Save state" in the test editor windoe to save your state information under whatever file name you want. In a later session, you can reload your saved states using "Session > Load state".<br />
<br />
==Generating a Symbol==<br />
Finally, we want to generate a symbol for our inverter. This symbol is needed if we want to use our inverter design inside another design (hierarchical design methodology). <br />
<br />
Select the schematic tab and choose "Create -> Create Cellview -> From Cellview". <br />
<br />
Press OK in the dialog that occurs.<br />
<br />
The pins should already be connected to the right positions in the symbol generator, so press OK here also and ths symbol editor will occur.<br />
<br />
Press the red X and delete the pre-created green square. Use the line tool and the circle tool to create the inverter symbol<br />
<br />
[[File:symbol.png|400px]]<br />
<br />
Save it by clicking the "Save and check" symbol or pressing 'shift+X'.<br />
<br />
[[Category:Mikroelektronikk]] [[Category:Integrated_Circuts]]</div>Put009http://ift.wiki.uib.no/index.php?title=Modelsim/Questa&diff=2674Modelsim/Questa2018-03-13T12:38:41Z<p>Put009: Updated a dead link</p>
<hr />
<div><!-- <br />
Mapping av alterabibliotek:<br />
<pre><br />
vmap cyclonev /prog/altera/vhdl_libs/cyclonev<br />
vmap lpm /prog/altera/vhdl_libs/lpm<br />
vmap altera /prog/altera/vhdl_libs/altera<br />
vmap altera_mf /prog/altera/vhdl_libs/altera_mf<br />
</pre><br />
--><br />
<br />
[[Simulering av VHDL]]<br />
<br />
[[VHDL Testbenk]]<br />
<br />
[[Synthese av VHDL]]<br />
<br />
[[Synthese av VHDL - Oppdatert]]<br />
<br />
== Referanselitteratur ==<br />
[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]<br />
<br />
<!--<br />
[http://www.ashenden.com.au/ Ashenden Designs] <br />
dead link<br />
--><br />
[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]<br />
<br />
[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]<br />
<br />
<!-- <br />
[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)] <br />
dead link<br />
--><br />
[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)]<br />
<br />
[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]<br />
<br />
[http://m.eet.com/media/1151614/23798-46098.pdf 10 tips for generating reusable VHDL]<br />
<br />
[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide]<br />
<br />
[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]<br />
<br />
[http://bitvis.no/products/bitvis-utility-library/ Bitvis utility library]<br />
<br />
[[Category:Mikroelektronikk]]</div>Put009http://ift.wiki.uib.no/index.php?title=Synthese_av_VHDL_-_Oppdatert&diff=2673Synthese av VHDL - Oppdatert2018-03-12T14:14:52Z<p>Put009: Link til intel si nedlastingsside for quartus og modelsim</p>
<hr />
<div>Obs! Fra Quartus Prime Handbook: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level<br />
timing simulation is supported only for the Stratix IV and Cyclone IV device families. Use<br />
TimeQuest static timing analysis rather than gate-level timing simulation.<br />
<br />
===Syntetiseringen av VHDL kode===<br />
<br />
Vi ønsker å syntisere koden for å lage beskrivelse av koden tilpasset en FPGA-chip. Vi skal først syntisere koden med Quartus. Deretter skal vi simulere denne koden og sammenligne med den opprinnelige koden uten timing-informasjon. Vi bruker en ALU som eksempel.<br />
<br />
Det er viktig at vi bruker Quartus og ModelSim fra samme utgivelse om vi ikke ønsker å kompilere våre egne simuleringsbibliotek. Du kan installere Quartus og ModelSim gratis og bruke lisens-server på UiB sitt nettverk. Vi bruker Quartus Prime 15.1 og ModelSim 10.4b. Quartus og Intel sin Modelsim versjon kan lastest ned [http://dl.altera.com/?product=modelsim_ae her].<br />
<br />
==Quartus==<br />
<br />
Lag et nytt prosjekt, kall det add_sub_alu og velg en passende mappe. Velg empty project, og deretter legg til add_sub_alu.vhd. Velg en CycloneIV-chip. Vi valgte EP4CE115F29. Det er chipen på Terasic DE2-115. Pass på at add_sub_alu.vhd er valgt som top-level og trykk så Start Compilation (Ctrl-L). Dette gjør at Quartus går gjennom alle stegene for å produsere filene vi er ute etter. I simulation/modelsim/ finner vi nå add_sub_alu.vho og add_sub_alu_vhd.sdo. Vho-filen(VHDL Output File) er filen som inneholder nå det opprinnelige designet, men også mange nye moduler med cycloneive-prefix. Disse entitetene beskriver ressurser på den fysiske FPGA-chipen. Sdo-filen(Standard Delay Format Output File) inneholder detaljer om delay fra hver modul på chippen. <br />
<br />
==Modelsim==<br />
<br />
Start opp Modelsim, lag nytt prosjekt og legg til vhdl fila for designet add_sub_alu.vhd og testbenken alu_tb.vhd. Så legg vi til fila som Quartus generte i prosjektdir til simulation/modelsim/add_sub_alu.vho.<br />
<br />
Den Quartus-genererte filen vil ha samme entitetsnavn som den opprinnelige, og vil derfor ikke kunne simuleres samtid. Vi endrer derfor den genererte filen til å ha entiteten 'add_sub_alu_synth' og architecturen 'structure' (i vårt tilfelle endret den seg til structure automatisk).<br />
<br />
Vi kan nå kompilere filene våre og deretter simulere testbenken. I testbenken vår ser vi at vi har kalt den syntiserte entiteten alu_synt. Dette skal vi bruke nå.<br />
<br />
==Simulering med timing==<br />
<br />
Velg Start Simulation - deretter work og alu_tb. Se så på SDF-fanen. Legg til add_sub_alu_vhd.sdo generert av Quartus tidligere. Under apply to region må du skrive:<br />
/alu_tb/alu_synt<br />
<br />
Dette er altså området vi ønsker at sdo-filen skal gi informasjon om. Trykk så OK.<br />
<br />
add wave *<br />
run -all<br />
<br />
Vi kan nå sammenligne utsignalene for den usyntiserte og den syntiserte ALU-komponenten.<br />
<br />
==Konklusjon==<br />
<br />
Vi ser at vi får masse feil før 50 ns. Dette skyldes at den opprinnelige komponenten ikke har definerte signaler før de første klokkeflankene, mens den syntiserte komponenten ikke kan ha udefinerte signaler. Senere får vi feil når signalene skifter. Dette skyldes at den syntiserte komponenten bruker lengre tid på å sende ut riktig signal, og vil også glitche mellom verdier før den stabiliserer seg på riktig verdi.<br />
<br />
==Kode==<br />
<br />
===Kode til add_sub_alu.vhdl===<br />
<br />
<pre><br />
LIBRARY ieee;<br />
USE ieee.std_logic_1164.All;<br />
USE ieee.std_logic_unsigned.all;<br />
<br />
ENTITY add_sub_alu IS<br />
PORT (clk, rst : IN std_logic;<br />
enable_in : IN std_logic;<br />
start : IN std_logic;<br />
enable : IN std_logic;<br />
do_add : IN std_logic;<br />
do_subtract : IN std_logic;<br />
do_hold : IN std_logic;<br />
data_in : IN std_logic_vector(3 DOWNTO 0);<br />
data_out : OUT std_logic_vector (3 DOWNTO 0) BUS);<br />
END add_sub_alu;<br />
<br />
ARCHITECTURE algorithm OF add_sub_alu IS<br />
TYPE states IS (hold, reset, add, subtract);<br />
SIGNAL state_var : states;<br />
SIGNAL reg, int_reg : std_logic_vector(3 DOWNTO 0);<br />
SIGNAL latched_data_in: std_logic_vector(3 DOWNTO 0);<br />
BEGIN<br />
<br />
latch: PROCESS (enable_in, data_in)is<br />
BEGIN<br />
IF (enable_in = '1') THEN<br />
latched_data_in <= data_in;<br />
END IF;<br />
END PROCESS latch;<br />
<br />
fsm: PROCESS (clk, rst) is<br />
BEGIN<br />
IF (rst = '0') THEN<br />
state_var <= reset;<br />
ELSIF (clk'EVENT AND clk = '1') THEN<br />
CASE state_var IS<br />
WHEN hold => IF (start = '1') THEN<br />
state_var <= reset;<br />
END IF;<br />
WHEN reset => IF (do_add = '1') THEN<br />
state_var <= add;<br />
ELSIF (do_subtract = '1') THEN<br />
state_var <= subtract;<br />
END IF;<br />
WHEN add => IF (do_hold = '1') THEN<br />
state_var <= hold;<br />
ELSIF (do_subtract = '1') THEN<br />
state_var <= subtract;<br />
END IF;<br />
WHEN subtract => IF (do_hold = '1') THEN<br />
state_var <= hold;<br />
ELSIF (do_add = '1') THEN<br />
state_var <= add;<br />
END IF;<br />
WHEN OTHERS => state_var <= reset;<br />
END CASE;<br />
END IF;<br />
END PROCESS fsm;<br />
<br />
alu: PROCESS (state_var, latched_data_in, reg)is<br />
BEGIN<br />
CASE state_var IS<br />
WHEN add => int_reg <= reg + latched_data_in;<br />
WHEN subtract => int_reg <= reg - latched_data_in;<br />
WHEN reset => int_reg <= "0000";<br />
WHEN hold => int_reg <= reg;<br />
WHEN OTHERS => int_reg <= reg;<br />
END CASE;<br />
END PROCESS alu;<br />
<br />
mem: PROCESS (clk) is<br />
BEGIN<br />
IF (clk'EVENT AND clk = '1') THEN<br />
reg <= int_reg;<br />
END IF;<br />
END PROCESS mem;<br />
<br />
tri: PROCESS (enable, reg) is<br />
BEGIN<br />
FOR i IN 3 DOWNTO 0 LOOP<br />
IF (enable = '1') THEN<br />
data_out(i) <= reg(i);<br />
ELSE<br />
data_out(i) <= 'Z';<br />
END IF;<br />
END LOOP;<br />
END PROCESS tri;<br />
<br />
END algorithm;<br />
</pre><br />
<br />
===Koden til alu_tb.vhdl===<br />
<br />
<pre><br />
library ieee;<br />
use ieee.std_logic_1164.all;<br />
library work;<br />
use work.all;<br />
<br />
entity alu_tb is<br />
end entity alu_tb;<br />
<br />
architecture struct of alu_tb is<br />
--Deklaring av signal som skal koblast til komponentane.<br />
--Alle innsignal er felles, medan vi har 2 forskjellige utsignal.<br />
signal clk, reset : std_logic;<br />
signal enable_in : std_logic;<br />
signal start : std_logic;<br />
signal enable : std_logic;<br />
signal do_add : std_logic;<br />
signal do_subtract : std_logic;<br />
signal do_hold : std_logic;<br />
signal data_in : std_logic_vector(3 downto 0);<br />
signal data_out : std_logic_vector(3 downto 0);<br />
signal data_out_synt : std_logic_vector(3 downto 0);<br />
<br />
begin<br />
<br />
--Deklarer komponenten alu.<br />
alu : entity add_sub_alu(algorithm)<br />
<br />
--Kobler signala til den opprinnelige komponenten.<br />
port map (<br />
clk => clk,<br />
rst => reset,<br />
enable_in => enable_in,<br />
start => start,<br />
enable => enable,<br />
do_add => do_add,<br />
do_subtract => do_subtract,<br />
do_hold => do_hold,<br />
data_in => data_in,<br />
data_out => data_out);<br />
<br />
--Deklarer komponenten alu_synt.<br />
alu_synt : entity add_sub_alu_synth(structure)<br />
<br />
--Kobler signala til den synthiserte komponenten.<br />
port map (<br />
clk => clk,<br />
rst => reset,<br />
enable_in => enable_in,<br />
start => start,<br />
enable => enable,<br />
do_add => do_add,<br />
do_subtract => do_subtract,<br />
do_hold => do_hold,<br />
data_in => data_in,<br />
data_out => data_out_synt);<br />
<br />
--Klokkegenerator<br />
clock_gen : process<br />
begin<br />
clk <= '0', '1' after 50 ns;<br />
wait for 100 ns;<br />
end process clock_gen;<br />
<br />
--Setter testvektorane.<br />
reset <= '0', '1' after 60 ns;<br />
enable <= '1', '0' after 900 ns;<br />
enable_in <= '1', '0' after 400 ns;<br />
start <= '1', '0' after 300 ns;<br />
do_add <= '1', '0' after 660 ns;<br />
do_subtract <= '0';<br />
do_hold <= '0';<br />
data_in <= X"3";<br />
<br />
--Test process for å samanlikne utsignala kvart nanosekund.<br />
test : process<br />
begin<br />
wait for 1 ns;<br />
assert (data_out = data_out_synt)<br />
report "Data ut er ulik"<br />
severity Error;<br />
end process test;<br />
<br />
end;<br />
<br />
</pre><br />
<br />
[[Category:Mikroelektronikk]] [[Category:VHDL]]</div>Put009http://ift.wiki.uib.no/index.php?title=XJTAG&diff=2672XJTAG2018-03-12T11:49:59Z<p>Put009: Updated path to XJTAG 3.5</p>
<hr />
<div>=XJEase and XJDeveloper Tutorial=<br />
<br />
You should run the tutorial at Program Files> XJTAG 3.5 > Help > XJEase and XJDeveloper tutorial. The program this tutorial is designed for is called XJDeveloper 3.5.<br />
This tutorial assumes you have a version 3.1 of the XJDemo board. In the help folder there is a turtorial.zip file with the files you're going to use. Unzip this to a new folder for your project.<br />
<br />
Below are pictures of versions 1.2 and 2.0 of the XJDemo board side-by-side so you can identify which you have. The main identifying feature of version 2.0 is its blue thumbwheel. On the 3.1 version you will see the name written on the card.<br />
<br />
<br />
[[Image:XJDemo v1.2.png|292px]][[Image:XJDemo v2.0.png|292px]]<br />
<br />
<br />
=Running the XJDemo version 2.0 demo on the XJDemo version 1.2 card=<br />
<br />
We are using version 1.2 XJDemo board (most likely version 1.2). The main functional differences are:<br />
# The RAM circuit is a Holtek HT6116 2Kx8 bit as opposed to the BS62LV256SC on the v2.0 board. Refer to the schematic for the pinmapping for page 11 of the tutorial. <br />
# The ADC is not available on the v1.2 board<br />
# The jumper between the Altera and Xilinx device is not present on the v1.2 board<br />
<br />
You can download the modified tutorial files from [http://web.ift.uib.no/~kjetil/wiki/XJTAG%20Demo%20Board.zip here].<br />
<br />
The tutorial aims to give you an understanding the process of creating an XJEase test system for a circuit, and the XJEase design philosophy. <br />
The tutorial can be navigated through the "Previous", "Home" and "Next" buttons at the top and bottom of each page in the tutorial.<br />
The structure of the tutorial is as follows: <br />
<br />
==Circuit description==<br />
The tutorial begins with a description of the XJDemo board and links to the data sheets for each of the components in the circuit. <br />
<br />
==Creating the project file==<br />
You will use XJDeveloper to create an XJEase description of the XJDemo board. This section explains how the various pieces of information are used, and what information can be gained from XJTAG automatically while creating the project file. <br />
<br />
==Running the connection test==<br />
We run a connection test and demonstrate various types of error detection using the XJDemo board. <br />
<br />
==Simple device testing==<br />
We create simple scripts to test the push buttons and LEDs. This illustrates the simplicity of programming in the XJEase language. <br />
<br />
==More complex device testing==<br />
We test the memory device, by creating a script that contains the read and write cycles for the device, along with a simple memory test that uses these functions. <br />
<br />
==Design reuse==<br />
Using a standard memory test and some standard IIC interface code, we quickly create some tests for the BS62LV256 static RAM and the EEPROM. <br />
==DFT Analysis==<br />
The demo script is analysed to check the coverage of the test code and find out where extra tests need to be applied to improve the testability of the board.<br />
<br />
=Additional resources=<br />
[[XJTAG_for_new_prototypes]]<br />
<br />
[[Category:Mikroelektronikk]]</div>Put009http://ift.wiki.uib.no/index.php?title=Bitvis_UVVM_VHDL_Verification_Component_Framework&diff=2671Bitvis UVVM VHDL Verification Component Framework2018-03-08T13:18:14Z<p>Put009: Corrected write and read signal names in set_inputs_passive and fixed dead link</p>
<hr />
<div>This wiki page is heavily based on the Powerpoint-presentation found [http://bitvis.no/media/15298/Simple_TB_step_by_step.pps here].<ref>UVVM LICENSE AGREEMENT<br />
IMPORTANT - READ BEFORE USING OR COPYING.<br />
THIS IS THE MIT LICENSE, see https://opensource.org/licenses/MIT<br />
------------------------------------------------------------------<br />
<br />
Copyright (c) 2016 by Bitvis AS<br />
<br />
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated<br />
documentation files (the "Software"), to deal in the Software without restriction, including without limitation<br />
the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, <br />
and to permit persons to whom the Software is furnished to do so, subject to the following conditions:<br />
<br />
The above copyright notice and this permission notice shall be included in all copies or substantial portions of <br />
the Software.<br />
<br />
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE<br />
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS<br />
OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR<br />
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</ref><br />
The presentation can also be found in the uvvm_util folder.<br />
<br />
== Introduction ==<br />
<br />
Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for <br />
verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the [https://github.com/UVVM/UVVM_All Bitvis github]. <br />
<br />
=== What's in the folders? ===<br />
[[File:20160302215840!1.png|thumb]]<br />
<br />
The download includes severals folders:<br />
* bitvis_irqc - example VHDL design + testbench<br />
* bitvis_uart - example VHDL design + testbench<br />
* bitvis_vip_sbi - Verification IP(VIP) for simple bus interface(SBI)<br />
* bitvis_vip_uart - VIP for UART TX and RX<br />
* uvvm_util - UVVM utility library - sufficient for simple testbenches<br />
* uvvm_vvc_framework - Framework for more advanced tutorials<br />
<br />
=== IRQC ===<br />
[[File:irqc.png|thumb]]<br />
The provided example VHDL design is a simple interrupt controller with several internal registers, a bus interface and some input and output signals.<br />
<br />
[[File:irqc2.png|350px]]<br />
<br />
== UVVM Utility Library - Testbench creation ==<br />
Copy the folders bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files.<br />
=== Generate TB entity with DUT instantiated ===<br />
Our TB entity can in many cases be generated from several tools. Notepad++ (among other) supports plugins that enables copying an entity and pasting it as an instantiation, and also as a complete testbench template. However, we will change some of our signals so that they fit the VIP SBI BFM. The signals to and from the CPU will be converted to t_sbi_if record, which is a type that includes all the SBI signals (cs, addr, rd, wr, wdata, ready and rdata).<br />
<br />
<pre><br />
--Standard libraries<br />
library IEEE;<br />
use IEEE.std_logic_1164.all;<br />
use IEEE.numeric_std.all;<br />
<br />
-- Library enabling control of the simulation from VHDL. Eg. std.env.stop<br />
library STD;<br />
use std.env.all;<br />
<br />
-- Obviously the UVVM library<br />
library uvvm_util;<br />
context uvvm_util.uvvm_util_context;<br />
<br />
-- We will use this library later when implementing the Bus Functional Model<br />
-- Includes among much else the record type t_sbi_if and many functions<br />
-- If other buses are used, you will have to change this library<br />
library bitvis_vip_sbi;<br />
use bitvis_vip_sbi.sbi_bfm_pkg.all;<br />
<br />
-- This file includes definitions of everything from registers to record types<br />
use work.irqc_pif_pkg.all;<br />
<br />
<br />
-- Test case entity<br />
entity irqc_tb is<br />
end entity;<br />
<br />
-- Test case architecture<br />
architecture func of irqc_tb is<br />
<br />
-- DSP interface and general control signals<br />
signal clk : std_logic := '0';<br />
signal arst : std_logic := '0';<br />
-- CPU interface<br />
-- t_sbi_if is from the verification IP SBI<br />
-- init_sbi_if_signals initialize the inputs to 0 and the outputs to Z<br />
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);<br />
<br />
-- Interrupt related signals<br />
signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');<br />
signal irq2cpu : std_logic := '0';<br />
signal irq2cpu_ack : std_logic := '0';<br />
<br />
begin<br />
<br />
-----------------------------------------------------------------------------<br />
-- Instantiate DUT<br />
-----------------------------------------------------------------------------<br />
i_irqc: entity work.irqc<br />
port map (<br />
-- DSP interface and general control signals<br />
clk => clk,<br />
arst => arst,<br />
-- CPU interface<br />
cs => sbi_if.cs, -- NOTICE THE SIGNALS ARE NOW SBI_IF<br />
addr => sbi_if.addr,<br />
wr => sbi_if.wena,<br />
rd => sbi_if.rena,<br />
din => sbi_if.wdata,<br />
dout => sbi_if.rdata,<br />
-- Interrupt related signals<br />
irq_source => irq_source,<br />
irq2cpu => irq2cpu,<br />
irq2cpu_ack => irq2cpu_ack<br />
);<br />
<br />
end func;<br />
</pre><br />
<br />
=== Add support process for clock generation ===<br />
We now have to add a support process that controls the clock. This has to allow enabling/disabling from the test sequencer. We add the following before "begin" in our architecture:<br />
<pre><br />
-- Added for clock generation<br />
signal clock_ena : boolean := false;<br />
<br />
constant C_CLK_PERIOD : time := 10 ns;<br />
<br />
procedure clock_gen(<br />
signal clock_signal : inout std_logic;<br />
signal clock_ena : in boolean;<br />
constant clock_period : in time<br />
) is<br />
variable v_first_half_clk_period : time := C_CLK_PERIOD / 2;<br />
begin<br />
loop<br />
if not clock_ena then<br />
wait until clock_ena;<br />
end if;<br />
wait for v_first_half_clk_period;<br />
clock_signal <= not clock_signal;<br />
wait for (clock_period - v_first_half_clk_period);<br />
clock_signal <= not clock_signal;<br />
end loop;<br />
end;<br />
</pre><br />
<br />
Our clock can now be activated from the test sequencer (this will be added in the next step):<br />
<pre><br />
-- After begin in the architecture<br />
clock_gen(clk, clock_ena, C_CLK_PERIOD);<br />
<br />
<br />
-- Inside the test sequencer process<br />
clock_ena <= true;<br />
</pre><br />
<br />
=== Add test sequencer process ===<br />
The next step is to add the test sequencer process. This process controls everything from initialization to termination of the simulation.<br />
<br />
<pre><br />
-- Set upt clock generator<br />
clock_gen(clk, clock_ena, C_CLK_PERIOD); <br />
<br />
------------------------------------------------<br />
-- PROCESS: p_main<br />
------------------------------------------------<br />
p_main : process<br />
-- The scope tells you where log messages originates - C_SCOPE tells us they originate from the default test sequencer scope<br />
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;<br />
-- This is where we will add some procedures later to simplify the tests<br />
<br />
begin<br />
<br />
--Print the configuration to the log<br />
report_global_ctrl(VOID);<br />
report_msg_id_panel(VOID);<br />
<br />
enable_log_msg(ALL_MESSAGES);<br />
--disable_log_msg<br />
--enable_log_msg(ID_LOG_HDR);<br />
<br />
log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE);<br />
------------------------------------------------------------<br />
clock_ena <= true; -- to start clock generator<br />
<br />
<br />
------------------------------------------------------------<br />
-- End the simulation<br />
wait for 1000 ns; -- to allow some time for completion<br />
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)<br />
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);<br />
<br />
--Finish the simulation<br />
std.env.stop;<br />
wait; -- to stop completely<br />
end process p_main;<br />
</pre><br />
<br />
==Simulation==<br />
We now have the skeleton of the testbench, which we will develop further. But now, let's see if everything works. Bitvis have created simulation scripts for the IRQC example that compiles everything we need, from the source files of the VHDL design, to the testbench (if you called the file irqc_tb.vhd and placed it in the tb-folder) and the SBI BFM and the UVVM library. Open up QuestaSim/ModelSim.<br />
Change directory to the script folder:<br />
<pre><br />
cd ~/phys321/bitviswiki/bitvis_irqc/script<br />
do compile_and_sim_all.do<br />
</pre><br />
<br />
This will present our result in the transcript windows, but also write _Log.txt file which includes all the information we have asked for. We see that we get the results from the following code:<br />
<pre><br />
report_global_ctrl(VOID);<br />
report_msg_id_panel(VOID);<br />
enable_log_msg(ALL_MESSAGES);<br />
log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE);<br />
report_alert_counters(FINAL);<br />
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);<br />
</pre><br />
Commenting these out will result in an empty log.<br />
<br />
== Verbosity control ==<br />
We want to able to control the amount of information in our logs, and the framework enables us to prioritize messages based on ID. This makes it easy to turn on or off the information we want.<br />
To turn on a specific ID<br />
<pre><br />
enable_log_msg(IDNAME);<br />
</pre><br />
<br />
Turn off:<br />
<pre><br />
disable_log_msg(IDNAME);<br />
</pre><br />
<br />
For writing a message to a certain log ID:<br />
<pre><br />
log(IDNAME, "MESSAGE HERE", C_SCOPE);<br />
</pre><br />
Remember that C_SCOPE just tells us that the message originated from the default scope and will look like "TB seq." in the log file.<br />
<br />
Exampled IDs:<br />
* ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers<br />
* ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)<br />
* ID_BFM, -- Used inside a BFM (to log BFM access)<br />
* ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled<br />
* ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER<br />
<br />
You'll find all the different ID's in the UVVM Utility Library Quick Reference or defined in uvvm_util/adaptions_pkg.vhd. This also where C_TB_SCOPE_DEFAULT is defined.<br />
<br />
== Implement first tests ==<br />
[[File:tb.png|thumb|upright=0.35]]<br />
We want to check and verify that our testbench is up and running and to verify our first tests of the DUT. This means that we have to able to set all our signals passive, apply a reset signal and then check the default outputs of the DUT.<br />
<br />
Instead of setting all our signals passive one-by-one in our test sequencer we declare a procedure in our p_main process(this is done before begin):<br />
<pre><br />
procedure set_inputs_passive(<br />
dummy : t_void) is --dummy variable is included only to allow calling the procedure with parenthesis for readability<br />
begin<br />
sbi_if.cs <= '0';<br />
sbi_if.addr <= (others => '0');<br />
sbi_if.wena <= '0';<br />
sbi_if.rena <= '0';<br />
sbi_if.wdata <= (others => '0');<br />
irq_source <= (others => '0');<br />
irq2cpu_ack <= '0';<br />
log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE);<br />
end;<br />
</pre><br />
<br />
Note that the procedure declaration also includes a dummy variable parameter. This means that we will be able to call the procedure with the more readable:<br />
<br />
<pre><br />
set_inputs_passive(VOID);<br />
</pre><br />
<br />
Rather than:<br />
<pre><br />
set_inputs_passive;<br />
</pre><br />
which is more ambigious.<br />
<br />
We may also would like to send pulses on different signals, f.ex. sending a pulse on our reset to see if it behaves like intended. We therefore can include a pulse procedure:<br />
<pre><br />
procedure pulse(<br />
signal target : inout std_logic_vector;<br />
constant pulse_value : in std_logic_vector;<br />
signal clock_signal : in std_logic;<br />
constant num_periods : in natural;<br />
constant msg : in string) is<br />
begin<br />
if num_periods > 0 then<br />
wait until falling_edge(clock_signal);<br />
target <= pulse_value;<br />
for i in 1 to num_periods loop<br />
wait until falling_edge(clock_signal);<br />
end loop;<br />
else<br />
target <= pulse_value;<br />
wait for 0 ns; -- Delta cycle only<br />
end if;<br />
target(target'range) <= (others => '0');<br />
log(ID_SEQUENCER_SUB, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & ". " & msg, C_SCOPE);<br />
end;<br />
</pre><br />
<br />
In the above example the test sequencer is required to inform the procedure of what value the pulse is to take. The call to the procedure would take the following form:<br />
<pre><br />
pulse(arst, 'Z', clk, 10, "Log message - Im pulsing the value 'Z'");<br />
</pre><br />
But a more specific overload can be created where pulse always takes value '1':<br />
<pre><br />
procedure pulse(<br />
signal target : inout std_logic;<br />
signal clock_signal : in std_logic;<br />
constant num_periods : in natural;<br />
constant msg : in string<br />
) is<br />
begin<br />
if num_periods > 0 then<br />
wait until falling_edge(clock_signal);<br />
target <= '1';<br />
for i in 1 to num_periods loop<br />
wait until falling_edge(clock_signal);<br />
end loop;<br />
else<br />
target <= '1';<br />
wait for 0 ns; -- Delta cycle only<br />
end if;<br />
target <= '0';<br />
log(ID_SEQUENCER_SUB, msg, C_SCOPE);<br />
end;<br />
</pre><br />
<br />
These procedures can now be called directly from our test sequence:<br />
<pre><br />
set_inputs_passive(VOID);<br />
pulse(arst, clk, 10, "pulsed reset-signal - active for 10T");<br />
</pre><br />
<br />
To check signal values we can use the built-in check function check_value():<br />
<pre><br />
check_value(irq2cpu, 'X', ERROR, "Interrupt to CPU must be default inactive", C_SCOPE);<br />
</pre><br />
The above call checks if the signal irq2cpu is 'X', and obviously fail if everything works correctly and gives the following message:<br />
<br />
[[File:error.png|700px]]<br />
<br />
If we want we can change the number of errors logged before the simulation stops:<br />
<pre><br />
set_alert_stop_limit(ERROR, 3);<br />
</pre><br />
<br />
We now have all the tools needed for the first tests in our sequencer:<br />
<pre><br />
set_inputs_passive(VOID);<br />
pulse(arst, clk, 10, "Pulsed reset-signal - active for 10T");<br />
<br />
check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt source", C_SCOPE);<br />
check_value(C_NUM_SOURCES <= 8, TB_WARNING, "This TB is only checking IRQC with up to 8 interrupt sources", C_SCOPE);<br />
<br />
log(ID_LOG_HDR, "Check defaults on output ports", C_SCOPE);<br />
------------------------------------------------------------<br />
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default inactive", C_SCOPE);<br />
check_value(sbi_if.rdata, x"00", ERROR, "Register data bus output must be default passive");<br />
</pre><br />
<br />
This will give us the following log:<br />
<br />
[[File:sim.png|800px]]<br />
<br />
This information may only interesting initially and for debug, and can be turned on or off by use of ID.<br />
<br />
== Subprograms ==<br />
Some of our testbench code will be repeated several times and the testbench may therefore benefit from creating several subprograms. Obvious examples for our IRQC is:<br />
- Register access<br />
- Signal checkers<br />
- Interrupt source pulsing?<br />
- Interrupt acknowledge pulsing?<br />
- (Report/log method)<br />
- (Alert-handling)<br />
- (reset, set_passive, ...)<br />
<br />
We've already created and declared set_passive and pulse procedures, but we could f.ex create overloads for UVVM procedures:<br />
<pre><br />
-- Log overloads for simplification<br />
procedure log(<br />
msg : string) is<br />
begin<br />
log(ID_SEQUENCER, msg, C_SCOPE);<br />
end;<br />
</pre><br />
<br />
Let's say that it is probable that we'll want to change the number of interrupt sources that the controller can handle. We will then want to able to easily change vectors to the appropriate size. One way is to declare procedures that can trim and fit vectors. This way we can simply change a constant to change the number of sources.<br />
<br />
<pre><br />
subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);<br />
<br />
-- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. reduce width)<br />
function trim(<br />
constant source : std_logic_vector;<br />
constant num_bits : positive := C_NUM_SOURCES)<br />
return t_irq_source is<br />
variable v_result : std_logic_vector(source'length-1 downto 0) := source;<br />
begin<br />
return v_result(num_bits-1 downto 0);<br />
end;<br />
<br />
-- Fit a given vector to the number of irq sources by masking with zeros above irq width<br />
function fit(<br />
constant source : std_logic_vector;<br />
constant num_bits : positive := C_NUM_SOURCES)<br />
return std_logic_vector is<br />
variable v_result : std_logic_vector(source'length-1 downto 0) := (others => '0');<br />
variable v_source : std_logic_vector(source'length-1 downto 0) := source;<br />
begin<br />
v_result(num_bits-1 downto 0) := v_source(num_bits-1 downto 0);<br />
return v_result;<br />
end;<br />
</pre><br />
<br />
All IRQC-dedicated subprograms should be declared locally, but more common (f.ex bus-specific) should be declared in common package that can be shared with other.<br />
<br />
== Register access ==<br />
To access the IRQC's registers we need to go through the actual process of writing and reading data from them. Fortunately, Bitvis have already taken the responsibility of writing the BFM for the SBI. This doesn't mean that we doesn't have to understand what's going on, since we'll have to write our own BFM's for other buses that we use(Avalon, AXI, etc). '''January 2017 Bitvis announced that they released VVC for Avalon-MM and AXI4-lite.''' So we should investigate the BFM procedures. We want to check register values:<br />
<pre><br />
procedure sbi_check (<br />
constant addr_value : in unsigned;<br />
constant data_exp : in std_logic_vector;<br />
constant alert_level : in t_alert_level := error;<br />
constant msg : in string;<br />
signal clk : in std_logic;<br />
signal cs : inout std_logic;<br />
signal addr : inout unsigned;<br />
signal rd : inout std_logic;<br />
signal wr : inout std_logic;<br />
signal ready : in std_logic;<br />
signal rdata : in std_logic_vector;<br />
constant scope : in string := C_SCOPE;<br />
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;<br />
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT<br />
) is<br />
constant proc_name : string := "sbi_check";<br />
constant proc_call : string := "sbi_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &<br />
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";<br />
-- Normalize to the DUT addr/data widths<br />
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=<br />
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);<br />
-- Helper variables<br />
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);<br />
variable v_check_ok : boolean;<br />
variable v_clk_cycles_waited : natural := 0;<br />
begin<br />
sbi_read(addr_value, v_data_value, msg, clk, cs, addr, rd, wr, ready, rdata, scope, msg_id_panel, config, proc_name);<br />
<br />
-- Compare values, but ignore any leading zero's if widths are different.<br />
-- Use ID_NEVER so that check_value method does not log when check is OK,<br />
-- log it here instead.<br />
v_check_ok := check_value(v_data_value, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);<br />
if v_check_ok then<br />
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & msg, scope, msg_id_panel);<br />
end if;<br />
end procedure;<br />
</pre><br />
<br />
We see that sbi_check() calls sbi_read() before it checks if the read value is the expected value.<br />
<br />
<pre><br />
procedure sbi_read (<br />
constant addr_value : in unsigned;<br />
variable data_value : out std_logic_vector;<br />
constant msg : in string;<br />
signal clk : in std_logic;<br />
signal cs : inout std_logic;<br />
signal addr : inout unsigned;<br />
signal rd : inout std_logic;<br />
signal wr : inout std_logic;<br />
signal ready : in std_logic;<br />
signal rdata : in std_logic_vector;<br />
constant scope : in string := C_SCOPE;<br />
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;<br />
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;<br />
constant proc_name : in string := "sbi_read" -- overwrite if called from other procedure like sbi_check<br />
) is<br />
constant proc_call : string := "sbi_read(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";<br />
-- Normalize to the DUT addr/data widths<br />
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=<br />
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);<br />
variable v_data_value : std_logic_vector(data_value'range);<br />
variable v_clk_cycles_waited : natural := 0;<br />
begin<br />
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);<br />
cs <= '1';<br />
wr <= '0';<br />
rd <= '1';<br />
addr <= v_normalised_addr;<br />
wait for config.clock_period;<br />
while (config.use_ready_signal and ready = '0') loop<br />
if v_clk_cycles_waited = 0 then<br />
log(config.id_for_bfm_wait, proc_call & " waiting for response (sbi ready=0)" & msg, scope, msg_id_panel);<br />
end if;<br />
wait for config.clock_period;<br />
v_clk_cycles_waited := v_clk_cycles_waited + 1;<br />
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,<br />
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, proc_call);<br />
end loop;<br />
<br />
cs <= '0';<br />
rd <= '0';<br />
v_data_value := rdata;<br />
data_value := v_data_value;<br />
if proc_name = "sbi_read" then<br />
log(config.id_for_bfm, proc_call & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & msg, scope, msg_id_panel);<br />
else<br />
-- Log will be handled by calling procedure (e.g. sbi_check)<br />
end if;<br />
end procedure;<br />
</pre><br />
<br />
We don't want to (and probably shouldnt) call the sbi_check and providing all the parameters each time. Some of this can be solved by the overloads with more standard parameters, and with our own check procedures declared locally in our testbench:<br />
<pre><br />
procedure check(<br />
constant addr_value : in natural;<br />
constant data_exp : in std_logic_vector;<br />
constant alert_level : in t_alert_level;<br />
constant msg : in string) is<br />
begin<br />
sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, alert_level, msg,<br />
clk, sbi_if, C_SCOPE);<br />
end;<br />
</pre><br />
<br />
The write procedure is also very handy and should be understood:<br />
<pre><br />
procedure sbi_write (<br />
constant addr_value : in unsigned;<br />
constant data_value : in std_logic_vector;<br />
constant msg : in string;<br />
signal clk : in std_logic;<br />
signal cs : inout std_logic;<br />
signal addr : inout unsigned;<br />
signal rd : inout std_logic;<br />
signal wr : inout std_logic;<br />
signal ready : in std_logic;<br />
signal wdata : inout std_logic_vector;<br />
constant scope : in string := C_SCOPE;<br />
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;<br />
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT<br />
) is<br />
constant proc_name : string := "sbi_write";<br />
constant proc_call : string := "sbi_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &<br />
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";<br />
-- Normalise to the DUT addr/data widths<br />
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=<br />
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);<br />
variable v_normalised_data : std_logic_vector(wdata'length-1 downto 0) :=<br />
normalize_and_check(data_value, wdata, ALLOW_NARROWER, "data_value", "sbi_core_in.wdata", msg);<br />
variable v_clk_cycles_waited : natural := 0;<br />
begin<br />
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);<br />
cs <= '1';<br />
wr <= '1';<br />
rd <= '0';<br />
addr <= v_normalised_addr;<br />
wdata <= v_normalised_data;<br />
<br />
wait for config.clock_period;<br />
while (config.use_ready_signal and ready = '0') loop<br />
if v_clk_cycles_waited = 0 then<br />
log(config.id_for_bfm_wait, proc_call & " waiting for response (sbi ready=0)" & msg, scope, msg_id_panel);<br />
end if;<br />
wait for config.clock_period;<br />
v_clk_cycles_waited := v_clk_cycles_waited + 1;<br />
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,<br />
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, proc_call);<br />
end loop;<br />
<br />
cs <= '0';<br />
wr <= '0';<br />
log(config.id_for_bfm, proc_call & " completed. " & msg, scope, msg_id_panel);<br />
end procedure;<br />
</pre><br />
<br />
We will create a local overload of this too:<br />
<pre><br />
procedure write(<br />
constant addr_value : in natural;<br />
constant data_value : in std_logic_vector;<br />
constant msg : in string) is<br />
begin<br />
sbi_write(to_unsigned(addr_value, sbi_if.addr'length), data_value, msg,<br />
clk, sbi_if, C_SCOPE);<br />
end;<br />
</pre><br />
<br />
All this enables us to handle transactions at a high level. See Bitvis documentation for how to write your own BFM and what it should include(sanity checks, etc).<br />
<br />
[[File:bfm.png|550px]]<br />
<br />
== Checking register write and read ==<br />
Now we're enabled to write to and read from the registers. The register addresses are defined in the IRQC package file irqc_pif_bkg.vhd. Notice that we also use the previously declared overloaded version of log() and fit().<br />
<br />
<pre><br />
log(ID_LOG_HDR, "Check register defaults and access (write + read)", C_SCOPE);<br />
------------------------------------------------------------<br />
log("\nChecking Register defaults");<br />
check(C_ADDR_IRR, x"00", ERROR, "IRR default");<br />
check(C_ADDR_IER, x"00", ERROR, "IER default");<br />
check(C_ADDR_IPR, x"00", ERROR, "IPR default");<br />
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED default");<br />
<br />
log("\nChecking Register Write/Read");<br />
write(C_ADDR_IER, fit(x"55"), "IER");<br />
check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback");<br />
write(C_ADDR_IER, fit(x"AA"), "IER");<br />
check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback");<br />
write(C_ADDR_IER, fit(x"00"), "IER");<br />
check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback");<br />
</pre><br />
<br />
This check will give us a nice log if everything turns out ok:<br />
<br />
[[File:sim2.png|700px]]<br />
<br />
However, if there's an error:<br />
<br />
[[File:error2.png|700px]]<br />
<br />
== Further tests ==<br />
<br />
Now that we've tested register read/write, we should test the trigger/clear mechanism. No further adding of procedures are necessary.<br />
<pre><br />
log(ID_LOG_HDR, "Check register trigger/clear mechanism", C_SCOPE);<br />
------------------------------------------------------------<br />
write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts");<br />
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR");<br />
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");<br />
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR");<br />
write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts");<br />
check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR");<br />
write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts");<br />
check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR");<br />
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");<br />
check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR");<br />
write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts");<br />
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR");<br />
</pre><br />
<br />
The UVVM Utility Library provides all necessary functions and procedures to do further tests. F.ex. we should send pulses on the irq_source signal to check if the design behaves correctly.<br />
<br />
<pre><br />
log(ID_LOG_HDR, "Check interrupt sources, IER, IPR and irq2cpu", C_SCOPE);<br />
------------------------------------------------------------<br />
log("\nChecking interrupts and IRR");<br />
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");<br />
pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T");<br />
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses");<br />
pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts");<br />
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");<br />
pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts");<br />
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");<br />
pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts");<br />
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses");<br />
write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts");<br />
pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts");<br />
check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses");<br />
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");<br />
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all");<br />
</pre><br />
<br />
=== Check stable ===<br />
Another test provided by UVVM is check_stable(). This function enables us to test if a signal is holding the same value for a minimum provided time. We must declare a variable that holds the time from which we want to test if the signal is stable:<br />
<br />
<pre><br />
v_time_stamp := now; -- time from which irq2cpu should be stable off until triggered<br />
</pre><br />
<br />
Later we're now able to test if the signal has been holding the same value the whole period:<br />
<pre><br />
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);<br />
</pre><br />
<br />
Remember to declare the variable in the process:<br />
<br />
<pre> <br />
variable v_time_stamp : time := 0 ns;<br />
</pre><br />
<br />
=== Await value ===<br />
To check if a signal gets the expected value within a specified time value we use await_vale(). The test below throws an error if irq2cpu doesn't obtain the value '1' within 0 ns(!). Therefore expected immediately:<br />
<br />
<pre><br />
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);<br />
</pre><br />
<br />
=== Other useful functions ===<br />
<br />
Check the UVVM Utility Library Quick Reference for syntax details.<br />
<br />
==== await_change() ====<br />
Expects and waits for a change on the given signal, inside a given time window. <br />
<br />
==== check_value_in_range() ====<br />
Throws an error of the signal value is outside the specified minimum and maximum values.<br />
<br />
== UVVM VVC ==<br />
Guide coming....<br />
<br />
== UVVM LICENCE AGREEMENT ==<br />
{{reflist}}<br />
<br />
[[Category:Mikroelektronikk]]</div>Put009