http://ift.wiki.uib.no/api.php?action=feedcontributions&user=Bhu006&feedformat=atomift - User contributions [en]2024-03-28T17:58:48ZUser contributionsMediaWiki 1.39.6http://ift.wiki.uib.no/index.php?title=MikroserverSetup&diff=2759MikroserverSetup2020-05-03T12:44:05Z<p>Bhu006: Included Windows X11 forwarding</p>
<hr />
<div>= Setup of connection to mikroservers= <br />
<br />
This setup process will allow you to connect to the mikroservers with one command without typing any password or long host names.<br />
<br />
There are 4 mikroservers at IFT, mikroserver1 through mikroserver4.<br />
<br />
== SSH key == <br />
To login to the server without having to type in your password every time, we can use SSH key pairs. The public key is stored on the server, and you have your private key stored on the UiB login server.<br />
<br />
To generate a key, type into the terminal <br />
ssh-keygen <br />
This will generate the files id_rsa and id_rsa.pub in the folder ~/.ssh, where the latter is the public key that needs to be stored on the server. Copy the key with your identity to either mikroserver (mikroserver3 is chosen in this example, but since the user environment is shared for each server, this will give you access to all the servers). You can do this manually, but the easiest way is to use the ssh-copy-id utility. NB: Replace USERNAME with your username<br />
ssh-copy-id USERNAME@mikroserver3.ift.uib.no<br />
You will be prompted your password. After the key is copied, you should be able to login with "ssh USERNAME@mikroserver3.ift.uib.no" without having to enter your password. <br />
<br />
== Connection aliases ==<br />
<br />
Now that you can login without typing your password, it is also convenient to set up aliases for the servers to connect quicker.<br />
<br />
To do this, type "gedit ~/.ssh/config" in the terminal.<br />
This will open up an empty file, and here you can store shorthand names and specific SSH settings for the connection, such as your username. <br />
Host mikroserver3<br />
HostName mikroserver3.ift.uib.no<br />
User USERNAME<br />
Port 22<br />
ForwardX11 yes<br />
ForwardX11Trusted yes<br />
Copy and repeat this for each server in the same file, remembering to change the hostname to the corresponding mikroserver for each entry. ForwardX11 allows you to launch software on the server itself, while displaying the GUI remotely to the lab PC. <br />
<br />
After saving the file, you should be able to simply write "ssh mikroserver3" in the terminal to login to mikroserver3. <br />
Note: If you are attempting to do this step remotely from the UiB login server you need to use a terminal-based editor like Vim, or connect to the login-server with <br />
ssh -Y USERNAME@login.uib.no<br />
to enable the use of graphical editors such as gedit.<br />
<br />
== Automatic sourcing ==<br />
There are two main files of sourcing scripts in a Linux environment. One is the file .bashrc, and the other is the file .profile. The difference in these is that the contents of .profile is executed upon login, and .bashrc is executed every time you access the terminal. .bashrc is not sourced to the system by itself upon login, so we need to source .bashrc in .profile manually to use it. This must be done after connecting to one of the mikroservers.<br />
<br />
echo "source ~/.bashrc" >> ~/.profile<br />
<br />
Scripts can be sourced either within .profile or .bashrc. This will make sure the scripts are loaded every time you log in, so you don't have to do it manually every time. <br />
<br />
== Accessing the lab software remotely on your private PC ==<br />
You do not need to set up a VPN to access the lab software from home. By connecting to the mikroservers through the UiB loginserver with X11 forwarding enabled, you can run the software from any network. You can do this directly on Linux/macOS by using SSH in the bash terminal. For Windows, you will need to download the X server software [https://sourceforge.net/projects/xming/ Xming] to enable X11 forwarding. This install comes with PuTTY, an SSH client we will use to connect to the Linux based UiB server. <br />
<br />
=== Linux/macOS ===<br />
The process is the same for both Linux and macOS, except that for macOS you first have to install the X11 server software named [https://www.xquartz.org/ XQuartz].<br />
Then, simply connect to the login server by typing<br />
ssh -Y USERNAME@login.uib.no<br />
<br />
The -Y enables trusted X11 forwarding. From here, you can "ssh mikroserver3" just as you would from the lab PC and run software. The steps described above (SSH keys and config files) can be repeated on your personal Linux/macOS PC to simplify connecting to the UiB loginserver. On Linux, the configuration file is located in "~/.ssh/config" just as on the server, while on macOS it is located in "/private/etc/ssh/ssh_config".<br />
<br />
=== Windows ===<br />
Install Xming and make sure you include PuTTY in the install. Run Xming. It will start minimized, and does not require any setup. <br />
When first opening PuTTY, you will be presented with this configuration menu. Fill in the hostname "login.uib.no", but don't connect yet.<br />
[[File:Puttylogin.png]]<br />
Navigate to Connection -> SSH -> X11, and check Enable X11 forwarding, and type in "localhost:0.0" as X display location.<br />
[[File:Puttyx11.png]]<br />
Return to Session, and make sure connection type is set to SSH. Press "Default Settings" and Save to save this configuration for later. Press Open to connect to the server. Enter your username and password, and now you should be in the Linux terminal for the UiB login server. Try to run "gedit" to confirm that you can run a graphical interface. From here you can ssh to the mikroservers and launch software as on the lab computer. Confirm by running gedit on the mikroserver as well to see that you can tunnel X11 through the login server correctly. <br />
<br />
== Add mikroserver as a folder on your pc ==<br />
<br />
Open up your home folder in Linux and in the bottom left corner click "Connect to Server" as shown in this picture:<br />
[[File:ConnectToServer.png|thumbnail]]<br />
<br />
as server address type:<br />
sftp://mikroserver3/home/USERNAME<br />
to add your homefolder on mikroserver as a folder on your local PC for easy access to your files (for example the [[Transistor_operating_point_printer]])<br />
To store this connection, right click the "mikroserver3"-folder and click "Add Bookmark". The next time you just click the bookmark to open it.<br />
<br />
=== Alternative way using scp/secure copy===<br />
If for some reason the above doesn’t work you can try this:<br />
* connect to your mikroserver (ssh mikroserver3)<br />
* locate the file you want to copy. i.e /home/USERNAME/picture.jpg<br />
* type this command<br />
scp picture.jpg USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
* this will copy the file to your home folder on any UiB machine<br />
* To copy a folder<br />
scp -r NameOfFolder USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
<br />
== Troubleshooting == <br />
* Make sure you have restarted your terminal (or source ~/.bashrc) if the commands doesn't work<br />
* You have to be either connected to the UiB loginserver or run the commands via the computers in the lab to be able to connect to the mikroservers<br />
* If you are using another shell like zsh or csh the aliases has to be in ~/.zshrc or ~/.cshrc instead of ~/.bashrc<br />
* Make sure you have replaced all the instances of USERNAME with your usename, i.e "abc0123"<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=File:Puttyx11.png&diff=2758File:Puttyx11.png2020-05-03T12:22:52Z<p>Bhu006: </p>
<hr />
<div></div>Bhu006http://ift.wiki.uib.no/index.php?title=File:Puttylogin.png&diff=2757File:Puttylogin.png2020-05-03T12:22:44Z<p>Bhu006: </p>
<hr />
<div></div>Bhu006http://ift.wiki.uib.no/index.php?title=MikroserverSetup&diff=2756MikroserverSetup2020-05-02T14:30:17Z<p>Bhu006: </p>
<hr />
<div>= Setup of connection to mikroservers= <br />
<br />
This setup process will allow you to connect to the mikroservers with one command without typing any password or host-names.<br />
<br />
There are 4 mikroservers at IFT, mikroserver1 through mikroserver4.<br />
<br />
== SSH key == <br />
To login to the server without having to type in your password every time, we can use SSH key pairs. The public key is stored on the server, and you have your private key stored on the UiB login server.<br />
<br />
To generate a key, type into the terminal <br />
ssh-keygen <br />
This will generate the files id_rsa and id_rsa.pub in the folder ~/.ssh, where the latter is the public key that needs to be stored on the server. Copy the key with your identity to either mikroserver (mikroserver3 is chosen in this example, but since the user environment is shared for each server, this will give you access to all the servers). You can do this manually, but the easiest way is to use the ssh-copy-id utility. NB: Replace USERNAME with your username<br />
ssh-copy-id USERNAME@mikroserver3.ift.uib.no<br />
You will be prompted your password. After the key is copied, you should be able to login with "ssh USERNAME@mikroserver3.ift.uib.no" without having to enter your password. <br />
<br />
== Connection aliases ==<br />
<br />
Now that you can login without typing your password, it is also convenient to set up host names for the servers to connect quicker.<br />
<br />
To do this, type "gedit ~/.ssh/config" in the terminal.<br />
This will open up an empty file, and here you can store short names and specific SSH settings for the connection, such as your username. <br />
Host mikroserver3<br />
HostName mikroserver3.ift.uib.no<br />
User USERNAME<br />
Port 22<br />
ForwardX11 yes<br />
ForwardX11Trusted yes<br />
Copy and repeat this for each server in the same file, remembering to change the hostname to the corresponding mikroserver for each entry. ForwardX11 allows you to launch software on the server itself, while displaying the GUI remotely to the lab PC. <br />
<br />
After saving the file, you should be able to simply write "ssh mikroserver3" in the terminal to login to mikroserver3. <br />
Note: If you are attempting to do this step remotely from the UiB login server you need to use a terminal-based editor like Vim, or connect to the login-server with <br />
ssh -Y USERNAME@login.uib.no<br />
to enable the use of graphical editors such as gedit.<br />
<br />
== Automatic sourcing ==<br />
There are two main files of sourcing scripts in a Linux environment. One is the file .bashrc, and the other is the file .profile. The difference in these is that the contents of .profile is executed upon login, and .bashrc is executed every time you access the terminal. .bashrc is not sourced to the system by itself upon login, so we need to source .bashrc in .profile manually to use it. This must be done after connecting to one of the mikroservers.<br />
<br />
echo "source ~/.bashrc" >> ~/.profile<br />
<br />
Scripts can be sourced either within .profile or .bashrc. This will make sure the scripts are loaded every time you log in, so you don't have to do it manually every time. <br />
<br />
== Accessing the lab software remotely on your private PC ==<br />
You do not need to set up a VPN to access the lab software from home. By connecting to the mikroservers through the UiB loginserver with X11 forwarding enabled, you can run the software from any network. You can do this directly on Linux/macOS by using SSH in the bash terminal. For Windows, you will need to download the TTY software [https://www.putty.org/ PuTTY] to enable X11 forwarding. <br />
<br />
=== Linux/macOS ===<br />
The process is the same for both Linux and macOS, except that for macOS you first have to install the X11 server software named XQuartz.<br />
Then, simply connect to the login server by typing<br />
ssh -Y USERNAME@login.uib.no<br />
<br />
The -Y enables trusted X11 forwarding. From here, you can "ssh mikroserver3" just as you would from the lab PC and run software. The steps described above (SSH keys and config files) can be repeated on your personal Linux/macOS PC to simplify connecting to the UiB loginserver. On Linux, the configuration file is located in "~/.ssh/config" just as on the server, while on macOS it is located in "/private/etc/ssh/ssh_config".<br />
<br />
=== Windows ===<br />
<br />
<br />
== Add mikroserver as a folder on your pc ==<br />
<br />
Open up your home folder in linux and in the bottom left corner click "Connect to Server" as shown in this picture:<br />
[[File:ConnectToServer.png|thumbnail]]<br />
<br />
as server address type:<br />
sftp://mikroserver3/home/USERNAME<br />
to add your homefolder on mikroserver as a folder on your local PC for easy access to your files (for example the [[Transistor_operating_point_printer]])<br />
To store this connection, right click the "mikroserver3"-folder and click "Add Bookmark". The next time you just click the bookmark to open it.<br />
<br />
=== Alternative way using scp/secure copy===<br />
If for some reason the above doesn’t work you can try this:<br />
* connect to your mikroserver (ssh mikroserver3)<br />
* locate the file you want to copy. i.e /home/USERNAME/picture.jpg<br />
* type this command<br />
scp picture.jpg USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
* this will copy the file to your home folder on any UiB machine<br />
* To copy a folder<br />
scp -r NameOfFolder USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
<br />
== Troubleshooting == <br />
* Make sure you have restarted your terminal (or source ~/.bashrc) if the commands doesn't work<br />
* You have to be either connected to the UiB loginserver or run the commands via the computers in the lab to be able to connect to the mikroservers<br />
* If you are using another shell like zsh or csh the aliases has to be in ~/.zshrc or ~/.cshrc instead of ~/.bashrc<br />
* Make sure you have replaced all the instances of USERNAME with your usename, i.e "abc0123"<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=Microelectronics_group&diff=2755Microelectronics group2020-05-02T14:26:50Z<p>Bhu006: </p>
<hr />
<div>== Øvinger og guider ==<br />
=== Mentor Graphics ===<br />
<br />
* [[Expedition PCB]] Komme i gang med kretskortutlegg ved hjelp av Expedition PCB<br />
<br />
* [[Modelsim/Questa]] Skrive og simulere VHDL-kode med Mentor Graphics ModelSim<br />
<br />
=== Cadence ===<br />
<br />
* [[Cadence Virtuoso]]<br />
<br />
=== Microsemi ===<br />
<br />
* [[SmartFusion2- AMBA APB, Custom Peripheral]] Making a custom peripheral for the AMBA APB bus<br />
<br />
=== Xilinx ===<br />
<br />
* [[Xilinx Vivado]] Tutorials for Xilinx Vivado<br />
<br />
* [[Xilinx SDK]] Tutorials for Xilinx Software Development Kit<br />
<br />
=== Annet ===<br />
* [[Bitvis UVVM VHDL Verification Component Framework]] <br />
<br />
* [[Tutorials]] Tutorials from the web<br />
<br />
* [[XJTAG]] Boundary Scan with XJTAG<br />
<br />
* [[XJDeveloper]] Innføring i XJDeveloper<br />
<br />
* [[FreeRTOS]] Free Real Time Operating System<br />
<br />
== Andre fagressurser og laboratorieveiledninger==<br />
<br />
* [[MikroserverSetup]] Oppsett av enkel tilkobling til mikroserverene<br />
<br />
* [[PHYS222]] Fagressurser for PHYS222 og PHYS223<br />
<br />
* [[PHYS321]] Fagressurser for PHYS321<br />
<br />
* [[Teknisk hjelp]] Teknisk hjelp for bruk av DAK-programvare<br />
<br />
* [[BGA lodding]] bruk av Martin 09.6 XL BGA lodding maskin (intern)<br />
<br />
* [[Reflow Soldering]] Use of Technoprint HA-02 reflow oven<br />
<br />
== Eldre øvinger og guider ==<br />
=== Mentor Graphics ===<br />
* [[IC studio]] Veiledning til IC-design ved hjelp av IC studio<br />
<br />
* [[IC studio - SPICE/Symbol Tutorial]] Relate a SPICE file to a Symbol<br />
<br />
* [[IC Station]] Tegne utlegg for integrerte kretser<br />
<br />
=== Annet ===<br />
* [[PCI-eksperiment]] Øving med HLT-RORC-prototypekort<br />
<br />
* [[Xilinx]] Øving i bruk av Xilinx Project Studio<br />
<br />
* [[SmartFusion2]] Oppsett og design med SF2<br />
<br />
* [[FLTK GUI]] Graphical User Interface using FLTK<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=MikroserverSetup&diff=2754MikroserverSetup2020-05-02T14:24:57Z<p>Bhu006: Fjernet oppsett av Cadence fra artikkelen siden det dekkes av andre artikler (og stoffet var utdatert). Ryddet opp generelt.</p>
<hr />
<div>= Setup of connection to mikroservers= <br />
<br />
This setup process will allow you to connect to the mikroservers with one command without typing any password or host-names.<br />
<br />
There are 4 mikroservers at IFT, mikroserver1 through mikroserver4.<br />
<br />
== SSH key == <br />
To login to the server without having to type in your password every time, we can use SSH key pairs. The public key is stored on the server, and you have your private key stored on the UiB login server.<br />
<br />
To generate a key, type into the terminal <br />
ssh-keygen <br />
This will generate the files id_rsa and id_rsa.pub in the folder ~/.ssh, where the latter is the public key that needs to be stored on the server. Copy the key with your identity to either mikroserver (mikroserver3 is chosen in this example, but since the user environment is shared for each server, this will give you access to all the servers). You can do this manually, but the easiest way is to use the ssh-copy-id utility. NB: Replace USERNAME with your username<br />
ssh-copy-id USERNAME@mikroserver3.ift.uib.no<br />
You will be prompted your password. After the key is copied, you should be able to login with "ssh USERNAME@mikroserver3.ift.uib.no" without having to enter your password. <br />
<br />
== Connection aliases ==<br />
<br />
Now that you can login without typing your password, it is also convenient to set up host names for the servers to connect quicker.<br />
<br />
To do this, type "gedit ~/.ssh/config" in the terminal.<br />
This will open up an empty file, and here you can store short names and specific SSH settings for the connection, such as your username. <br />
Host mikroserver3<br />
HostName mikroserver3.ift.uib.no<br />
User USERNAME<br />
Port 22<br />
ForwardX11 yes<br />
ForwardX11Trusted yes<br />
Copy and repeat this for each server in the same file, remembering to change the hostname to the corresponding mikroserver for each entry. ForwardX11 allows you to launch software on the server itself, while displaying the GUI remotely to the lab PC. <br />
<br />
After saving the file, you should be able to simply write "ssh mikroserver3" in the terminal to login to mikroserver3. <br />
Note: If you are attempting to do this step remotely from the UiB login server you need to use a terminal-based editor like Vim, or connect to the login-server with <br />
ssh -Y USERNAME@login.uib.no<br />
to enable the use of graphical editors such as gedit.<br />
<br />
== Automatic sourcing ==<br />
There are two main files of sourcing scripts in a Linux environment. One is the file .bashrc, and the other is the file .profile. The difference in these is that the contents of .profile is executed upon login, and .bashrc is executed every time you access the terminal. .bashrc is not sourced to the system by itself upon login, so we need to source .bashrc in .profile manually to use it. This must be done after connecting to one of the mikroservers.<br />
<br />
echo "source ~/.bashrc" >> ~./profile<br />
<br />
Scripts can be sourced either within .profile or .bashrc. This will make sure the scripts are loaded every time you log in, so you don't have to do it manually every time. <br />
<br />
== Accessing the lab software remotely on your private PC ==<br />
You do not need to set up a VPN to access the lab software from home. By connecting to the mikroservers through the UiB loginserver with X11 forwarding enabled, you can run the software from any network. You can do this directly on Linux/macOS by using SSH in the bash terminal. For Windows, you will need to download the TTY software [https://www.putty.org/ PuTTY] to enable X11 forwarding. <br />
<br />
=== Linux/macOS ===<br />
The process is the same for both Linux and macOS, except that for macOS you first have to install the X11 server software named XQuartz.<br />
Then, simply connect to the login server by typing<br />
ssh -Y USERNAME@login.uib.no<br />
<br />
The -Y enables trusted X11 forwarding. From here, you can "ssh mikroserver3" just as you would from the lab PC and run software. The steps described above (SSH keys and config files) can be repeated on your personal Linux/macOS PC to simplify connecting to the UiB loginserver. On Linux, the configuration file is located in "~/.ssh/config" just as on the server, while on macOS it is located in "/private/etc/ssh/ssh_config".<br />
<br />
=== Windows ===<br />
<br />
<br />
== Add mikroserver as a folder on your pc ==<br />
<br />
Open up your home folder in linux and in the bottom left corner click "Connect to Server" as shown in this picture:<br />
[[File:ConnectToServer.png|thumbnail]]<br />
<br />
as server address type:<br />
sftp://mikroserver3/home/USERNAME<br />
to add your homefolder on mikroserver as a folder on your local PC for easy access to your files (for example the [[Transistor_operating_point_printer]])<br />
To store this connection, right click the "mikroserver3"-folder and click "Add Bookmark". The next time you just click the bookmark to open it.<br />
<br />
=== Alternative way using scp/secure copy===<br />
If for some reason the above doesn’t work you can try this:<br />
* connect to your mikroserver (ssh mikroserver3)<br />
* locate the file you want to copy. i.e /home/USERNAME/picture.jpg<br />
* type this command<br />
scp picture.jpg USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
* this will copy the file to your home folder on any UiB machine<br />
* To copy a folder<br />
scp -r NameOfFolder USERNAME@login.uib.no:path/to/folder/to/copy/to<br />
<br />
== Troubleshooting == <br />
* Make sure you have restarted your terminal (or source ~/.bashrc) if the commands doesn't work<br />
* You have to be either connected to the UiB loginserver or run the commands via the computers in the lab to be able to connect to the mikroservers<br />
* If you are using another shell like zsh or csh the aliases has to be in ~/.zshrc or ~/.cshrc instead of ~/.bashrc<br />
* Make sure you have replaced all the instances of USERNAME with your usename, i.e "abc0123"<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=Layout_XL_and_IHP_SG13S&diff=2753Layout XL and IHP SG13S2020-05-01T11:11:03Z<p>Bhu006: </p>
<hr />
<div>= Before starting layout =<br />
<br />
Read the Design Kit User Guide. The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/doc/pdf" on the microserver.<br />
Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.<br />
<br />
[[File:SG13 Design Kit User Guide.pdf]]<br />
<br />
[[File:SG13 Layout rules.pdf]]<br />
<br />
[[File:Documentation.png|200px]]<br />
<br />
If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed"). <br />
<br />
= Layout XL =<br />
<br />
From the schematic click Launch -> Layout XL to open the layout environment.<br />
<br />
[[File:layout.png|200px]] [[File:layout2.png|200px]]<br />
<br />
Layout XL opens with a new black empty canvas. The schematic window also opens. This is very useful as when we add our devices in the layout we can see which device they represent in the schematic as they get highlighted.<br />
<br />
Before anything you must define some options to avoid a lot of DRC-errors down the line. In the Layout Rules-document we read what our drawing-grid restrictions are (bottom of page 10). In Layout XL press E to open the Display Options-window. Remember that all size-values are in micrometers. Set the X and Y Snap Spacing to reflect the grid rules. Now press Shift-E to open the Layout Editor Options. Set gravity on(you can turn this off later with the g-key if you dont like it), and aperture around 0.1. This defines the the distance before snapping to another object etc.<br />
<br />
[[File:grid.png|200px]] [[File:gravity.png|200px]]<br />
<br />
= Generate from source =<br />
<br />
IHP has already defined transistors, pins, etc. for different sized, so it is not needed to draw these from scratch. You should, however, dissect them to understand how they work. To place all the devices from the schematic press Connectivity -> Generate -> All From Source. In this window we define which of our devices we want to place, the I/O pins, PR boundary (the area which our cell must be within) and floorplan settings (if needed). For our cell we need to change the IO-pins. We want the gnd and bit-lines to be vertical, and vdd and word-lines to be horizontal. This means that they will intersect each other and must be in different layers. We also want two gnd-pins which also can be defined here. Remember to uncheck Create under the sub!-pin since this is not needed. <br />
<br />
Change the Label options to a smaller font size (about 0.1 is ok). Click OK to see the results.<br />
<br />
[[File:result.png|600px]]<br />
<br />
The purple box is the PR boundary in which are layout must be contained. Notice how the ntap1 is highlighted in the schematic when clicked in the layout window.<br />
<br />
= Pin Placement =<br />
<br />
Press Place -> Pin Placement. This opens a windows that lets us define the position of our pins. This is very helpful to line up our design. Remember that the positions may be tweaked later.<br />
<br />
[[File:pinplacement.png|400px]]<br />
<br />
= Placing devices =<br />
<br />
If you are extremely lazy you can autoplace the components with Place -> Custom Digital -> Placer. This, however, will probably not give you the desired result. To help you place the the devices correctly it is helpful to see which devices that connect to each other and how. This is accomplished with Connectivity -> Nets -> Show/Hide All Incomplete Nets. This will give you a all the nets that are uncompleted and can be very daunting. However, you can use Ctrl++ (that is Ctrl and +-key ) to turn on or off the nets for the selected device. <br />
<br />
F4 switches between Full and Partial Select. Partial Select means that we are able to select individual pieces of a device, e.g. if we want to stretch a part.<br />
<br />
[[File:partial.png|50px]] [[File:partial2.png|50px]]<br />
<br />
== DRD ==<br />
[[File:DRDbuttons.png|50px]]<br />
<br />
DRD stands for Dynamic Design Rule Checking and are helpful while laying out your design. DRD Enforce On prevents you from doing anything that breaks the rules, and DRD Notify tells you if what you are doing is illegal. Image below shows example of DRD Notify.<br />
<br />
[[File:DRD.png|200px]]<br />
<br />
== Drawing ==<br />
<br />
To draw rectangles (e.g. NWell) choose the wanted layer on the left side then press R. To create a connection between to nodes you can either create a wire (Ctrl+W) or a path (P). A wire automatically helps with choosing layer, and may also be used to create vias to another layer by left-clicking.<br />
<br />
A complete layout could look something like this:<br />
<br />
[[File:sram.png|600px]]<br />
<br />
Note that there is a specified minimum enclosure in the design rules for vias between polysilicon and metal. This is because during the manufacturing process, the polysilicon and metal layers are created separately and the alignment is not perfect, so the polysilicon connection must be slightly larger to accommodate the potential offset between these layers. Enclosures can be seen by the polysilicon squares on the vias connecting the Q and Q_B lines in the design above. To set a via enclosure size, right click the via and go to properties. On the bottom, there is a setting for GatPoly enclosure. You must set each direction separately. <br />
<br />
= DRC =<br />
<br />
Run DRC by pressing Assura -> Run DRC. Make sure technology is SG13_dev and the Rule Set is default. Read about the different switches in the user guide (e.g. antenna-rules etc). If everything is ok this message should appear:<br />
<br />
[[File:drcok.png|200px]]<br />
<br />
The DRC should also be run for Density. See IHP user guide for how to produce dummy metal to fill the design.<br />
<br />
= LVS =<br />
<br />
This is covered in chapter 12 of the user guide.<br />
<br />
Run LVS by pressing Assura -> Run LVS. This will give you a match if the schematic and the layout match each other, or you will get some errors.<br />
<br />
[[File:LVS_summary.png|200px]]<br />
<br />
= Parasitic extraction QRC =<br />
<br />
This is covered in chapter 14 of the user guide. Before you run the QRC, the LVS has to match.<br />
<br />
To do an extraction of your circuit click Assura -> Run Quantus. In "Setup Dir" make sure the path is set to "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/Assura_SG13/qrc", where the technology files for the qrc run is. Set the "Parasitic Res Component" to "presistor ivpcell SG13_dev" and the "Parasitic Cap Component" to "pcapacitor ivpcell SG13_dev". Open the Extraction tab and set your ground net (gnd!) in the "Reference node" box. Then run the QRC by pressing OK.<br />
<br />
[[File:ASSURA_QRC.png|400px]]<br />
<br />
This should give you an extracted design called "av_extracted" in the cell of the library. This can be checked and viewed from the library manager. In this picture the extracted cell is a SRAM with bitline conditioning and a write driver.<br />
<br />
[[File:Extracted_layout_SRAM_with_bt_wd.png|400px]]<br />
<br />
= Post layout simulation =<br />
<br />
In the library manager make an copy of the SRAM cell, to use as a test bench cell. Click file -> new -> Cell View and make an config file in your new test bench cell. Use "config" as the type, and click "ok". In the new window click on the "Use template" and select "AMS", and click "ok". Then edit the view list and add "av_extracted" with the add box. Clicking ok will then bring you to the hierarchy editor.<br />
<br />
Then you need a test bench schematic. In your copied schematic you will have the whole SRAM or different symbols making up the SRAM, but for the simulation there should only be a symbol that matches the extracted layout. So go back to the schematic in the SRAM cell and make one symbol out of it. Put this symbol into the test bench schematic, and add the pins that are needed.<br />
<br />
Go back to the hierarchy editor and change the View to your test bench schematic and update the hierarchy. Then right click on the "view found" for the SRAM from the SRAM cell, and select the av_extracted.<br />
<br />
[[File:Hierarchy_editor.png|400px]]<br />
<br />
Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=Layout_XL_and_IHP_SG13S&diff=2752Layout XL and IHP SG13S2020-04-29T12:49:38Z<p>Bhu006: </p>
<hr />
<div>= Before starting layout =<br />
<br />
Read the Design Kit User Guide. The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/doc/pdf" on the microserver.<br />
Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.<br />
<br />
[[File:SG13 Design Kit User Guide.pdf]]<br />
<br />
[[File:SG13 Layout rules.pdf]]<br />
<br />
[[File:Documentation.png|200px]]<br />
<br />
If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed"). <br />
<br />
= Layout XL =<br />
<br />
From the schematic click Launch -> Layout XL to open the layout environment.<br />
<br />
[[File:layout.png|200px]] [[File:layout2.png|200px]]<br />
<br />
Layout XL opens with a new black empty canvas. The schematic window also opens. This is very useful as when we add our devices in the layout we can see which device they represent in the schematic as they get highlighted.<br />
<br />
Before anything you must define some options to avoid a lot of DRC-errors down the line. In the Layout Rules-document we read what our drawing-grid restrictions are (bottom of page 10). In Layout XL press E to open the Display Options-window. Remember that all size-values are in micrometers. Set the X and Y Snap Spacing to reflect the grid rules. Now press Shift-E to open the Layout Editor Options. Set gravity on(you can turn this off later with the g-key if you dont like it), and aperture around 0.1. This defines the the distance before snapping to another object etc.<br />
<br />
[[File:grid.png|200px]] [[File:gravity.png|200px]]<br />
<br />
= Generate from source =<br />
<br />
IHP has already defined transistors, pins, etc. for different sized, so it is not needed to draw these from scratch. You should, however, dissect them to understand how they work. To place all the devices from the schematic press Connectivity -> Generate -> All From Source. In this window we define which of our devices we want to place, the I/O pins, PR boundary (the area which our cell must be within) and floorplan settings (if needed). For our cell we need to change the IO-pins. We want the gnd and bit-lines to be vertical, and vdd and word-lines to be horizontal. This means that they will intersect each other and must be in different layers. We also want two gnd-pins which also can be defined here. Remember to uncheck Create under the sub!-pin since this is not needed. <br />
<br />
Change the Label options to a smaller font size (about 0.1 is ok). Click OK to see the results.<br />
<br />
[[File:result.png|600px]]<br />
<br />
The purple box is the PR boundary in which are layout must be contained. Notice how the ntap1 is highlighted in the schematic when clicked in the layout window.<br />
<br />
= Pin Placement =<br />
<br />
Press Place -> Pin Placement. This opens a windows that lets us define the position of our pins. This is very helpful to line up our design. Remember that the positions may be tweaked later.<br />
<br />
[[File:pinplacement.png|400px]]<br />
<br />
= Placing devices =<br />
<br />
If you are extremely lazy you can autoplace the components with Place -> Custom Digital -> Placer. This, however, will probably not give you the desired result. To help you place the the devices correctly it is helpful to see which devices that connect to each other and how. This is accomplished with Connectivity -> Nets -> Show/Hide All Incomplete Nets. This will give you a all the nets that are uncompleted and can be very daunting. However, you can use Ctrl++ (that is Ctrl and +-key ) to turn on or off the nets for the selected device. <br />
<br />
F4 switches between Full and Partial Select. Partial Select means that we are able to select individual pieces of a device, e.g. if we want to stretch a part.<br />
<br />
[[File:partial.png|50px]] [[File:partial2.png|50px]]<br />
<br />
== DRD ==<br />
[[File:DRDbuttons.png|50px]]<br />
<br />
DRD stands for Dynamic Design Rule Checking and are helpful while laying out your design. DRD Enforce On prevents you from doing anything that breaks the rules, and DRD Notify tells you if what you are doing is illegal. Image below shows example of DRD Notify.<br />
<br />
[[File:DRD.png|200px]]<br />
<br />
== Drawing ==<br />
<br />
To draw rectangles (e.g. NWell) choose the wanted layer on the left side then press R. To create a connection between to nodes you can either create a wire (Ctrl+W) or a path (P). A wire automatically helps with choosing layer, and may also be used to create vias to another layer by left-clicking.<br />
<br />
A complete layout could look something like this:<br />
<br />
[[File:sram.png|600px]]<br />
<br />
= DRC =<br />
<br />
Run DRC by pressing Assura -> Run DRC. Make sure technology is SG13_dev and the Rule Set is default. Read about the different switches in the user guide (e.g. antenna-rules etc). If everything is ok this message should appear:<br />
<br />
[[File:drcok.png|200px]]<br />
<br />
The DRC should also be run for Density. See IHP user guide for how to produce dummy metal to fill the design.<br />
<br />
= LVS =<br />
<br />
This is covered in chapter 12 of the user guide.<br />
<br />
Run LVS by pressing Assura -> Run LVS. This will give you a match if the schematic and the layout match each other, or you will get some errors.<br />
<br />
[[File:LVS_summary.png|200px]]<br />
<br />
= Parasitic extraction QRC =<br />
<br />
This is covered in chapter 14 of the user guide. Before you run the QRC, the LVS has to match.<br />
<br />
To do an extraction of your circuit click Assura -> Run Quantus. In "Setup Dir" make sure the path is set to "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/Assura_SG13/qrc", where the technology files for the qrc run is. Set the "Parasitic Res Component" to "presistor ivpcell SG13_dev" and the "Parasitic Cap Component" to "pcapacitor ivpcell SG13_dev". Open the Extraction tab and set your ground net (gnd!) in the "Reference node" box. Then run the QRC by pressing OK.<br />
<br />
[[File:ASSURA_QRC.png|400px]]<br />
<br />
This should give you an extracted design called "av_extracted" in the cell of the library. This can be checked and viewed from the library manager. In this picture the extracted cell is a SRAM with bitline conditioning and a write driver.<br />
<br />
[[File:Extracted_layout_SRAM_with_bt_wd.png|400px]]<br />
<br />
= Post layout simulation =<br />
<br />
In the library manager make an copy of the SRAM cell, to use as a test bench cell. Click file -> new -> Cell View and make an config file in your new test bench cell. Use "config" as the type, and click "ok". In the new window click on the "Use template" and select "AMS", and click "ok". Then edit the view list and add "av_extracted" with the add box. Clicking ok will then bring you to the hierarchy editor.<br />
<br />
Then you need a test bench schematic. In your copied schematic you will have the whole SRAM or different symbols making up the SRAM, but for the simulation there should only be a symbol that matches the extracted layout. So go back to the schematic in the SRAM cell and make one symbol out of it. Put this symbol into the test bench schematic, and add the pins that are needed.<br />
<br />
Go back to the hierarchy editor and change the View to your test bench schematic and update the hierarchy. Then right click on the "view found" for the SRAM from the SRAM cell, and select the av_extracted.<br />
<br />
[[File:Hierarchy_editor.png|400px]]<br />
<br />
Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=Layout_XL_and_IHP_SG13S&diff=2751Layout XL and IHP SG13S2020-04-27T09:48:07Z<p>Bhu006: </p>
<hr />
<div>= Before starting layout =<br />
<br />
Read the Design Kit User Guide. The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/doc/pdf" on the microserver.<br />
Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.<br />
<br />
[[File:SG13 Design Kit User Guide.pdf]]<br />
<br />
[[File:SG13 Layout rules.pdf]]<br />
<br />
[[File:Documentation.png|200px]]<br />
<br />
If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed"). <br />
<br />
= Layout XL =<br />
<br />
From the schematic click Launch -> Layout XL to open the layout environment.<br />
<br />
[[File:layout.png|200px]] [[File:layout2.png|200px]]<br />
<br />
Layout XL opens with a new black empty canvas. The schematic window also opens. This is very useful as when we add our devices in the layout we can see which device they represent in the schematic as they get highlighted.<br />
<br />
Before anything you must define some options to avoid a lot of DRC-errors down the line. In the Layout Rules-document we read what our drawing-grid restrictions are (bottom of page 10). In Layout XL press E to open the Display Options-window. Remember that all size-values are in micrometers. Set the X and Y Snap Spacing to reflect the grid rules. Now press Shift-E to open the Layout Editor Options. Set gravity on(you can turn this off later with the g-key if you dont like it), and aperture around 0.1. This defines the the distance before snapping to another object etc.<br />
<br />
[[File:grid.png|200px]] [[File:gravity.png|200px]]<br />
<br />
= Generate from source =<br />
<br />
IHP has already defined transistors, pins, etc. for different sized, so it is not needed to draw these from scratch. You should, however, dissect them to understand how they work. To place all the devices from the schematic press Connectivity -> Generate -> All From Source. In this window we define which of our devices we want to place, the I/O pins, PR boundary (the area which our cell must be within) and floorplan settings (if needed). For our cell we need to change the IO-pins. We want the gnd and bit-lines to be vertical, and vdd and word-lines to be horizontal. This means that they will intersect each other and must be in different layers. We also want two gnd-pins which also can be defined here. Remember to uncheck Create under the sub!-pin since this is not needed. <br />
<br />
Change the Label options to a smaller font size (about 0.1 is ok). Click OK to see the results.<br />
<br />
[[File:result.png|600px]]<br />
<br />
The purple box is the PR boundary in which are layout must be contained. Notice how the ntap1 is highlighted in the schematic when clicked in the layout window.<br />
<br />
= Pin Placement =<br />
<br />
Press Place -> Pin Placement. This opens a windows that lets us define the position of our pins. This is very helpful to line up our design. Remember that the positions may be tweaked later.<br />
<br />
[[File:pinplacement.png|400px]]<br />
<br />
= Placing devices =<br />
<br />
If you are extremely lazy you can autoplace the components with Place -> Custom Digital -> Placer. This, however, will probably not give you the desired result. To help you place the the devices correctly it is helpful to see which devices that connect to each other and how. This is accomplished with Connectivity -> Nets -> Show/Hide All Incomplete Nets. This will give you a all the nets that are uncompleted and can be very daunting. However, you can use Ctrl++ (that is Ctrl and +-key ) to turn on or off the nets for the selected device. <br />
<br />
F4 switches between Full and Partial Select. Partial Select means that we are able to select individual pieces of a device, e.g. if we want to stretch a part.<br />
<br />
[[File:partial.png|50px]] [[File:partial2.png|50px]]<br />
<br />
== DRD ==<br />
[[File:DRDbuttons.png|50px]]<br />
<br />
DRD stands for Dynamic Design Rule Checking and are helpful while laying out your design. DRD Enforce On prevents you from doing anything that breaks the rules, and DRD Notify tells you if what you are doing is illegal. Image below shows example of DRD Notify.<br />
<br />
[[File:DRD.png|200px]]<br />
<br />
== Drawing ==<br />
<br />
To draw rectangles (e.g. NWell) choose the wanted layer on the left side then press R. To create a connection between to nodes you can either create a wire (Ctrl+W) or a path (P). A wire automatically helps with choosing layer, and may also be used to create vias to another layer by left-clicking.<br />
<br />
A complete layout could look something like this:<br />
<br />
[[File:sram.png|600px]]<br />
<br />
= DRC =<br />
<br />
Run DRC by pressing Assura -> Run DRC. Make sure technology is SG13_dev and the Rule Set is default. Read about the different switches in the user guide (e.g. antenna-rules etc). If everything is ok this message should appear:<br />
<br />
[[File:drcok.png|200px]]<br />
<br />
The DRC should also be run for Density. See IHP user guide for how to produce dummy metal to fill the design.<br />
<br />
= LVS =<br />
<br />
This is covered in chapter 12 of the user guide.<br />
<br />
Run LVS by pressing Assura -> Run LVS. This will give you a match if the schematic and the layout match each other, or you will get some errors.<br />
<br />
[[File:LVS_summary.png|200px]]<br />
<br />
= Parasitic extraction QRC =<br />
<br />
This is covered in chapter 14 of the user guide. Before you run the QRC, the LVS has to match.<br />
<br />
To do an extraction of your circuit click Assura -> Run Quantus QRC. In "Setup Dir" make sure the path is set to "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/Assura_SG13/qrc", where the technology files for the qrc run is. Set the "Parasitic Res Component" to "presistor ivpcell SG13_dev" and the "Parasitic Cap Component" to "pcapacitor ivpcell SG13_dev". The run the QRC.<br />
<br />
[[File:ASSURA_QRC.png|400px]]<br />
<br />
This should give you an extracted design called "av_extracted" in the cell of the library. This can be checked and viewed from the library manager. In this picture the extracted cell is a SRAM with bitline conditioning and a write driver.<br />
<br />
[[File:Extracted_layout_SRAM_with_bt_wd.png|400px]]<br />
<br />
= Post layout simulation =<br />
<br />
In the library manager make an copy of the SRAM cell, to use as a test bench cell. Click file -> new -> Cell View and make an config file in your new test bench cell. Use "config" as the type, and click "ok". In the new window click on the "Use template" and select "AMS", and click "ok". Then edit the view list and add "av_extracted" with the add box. Clicking ok will then bring you to the hierarchy editor.<br />
<br />
Then you need a test bench schematic. In your copied schematic you will have the whole SRAM or different symbols making up the SRAM, but for the simulation there should only be a symbol that matches the extracted layout. So go back to the schematic in the SRAM cell and make one symbol out of it. Put this symbol into the test bench schematic, and add the pins that are needed.<br />
<br />
Go back to the hierarchy editor and change the View to your test bench schematic and update the hierarchy. Then right click on the "view found" for the SRAM from the SRAM cell, and select the av_extracted.<br />
<br />
[[File:Hierarchy_editor.png|400px]]<br />
<br />
Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.<br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=Synthese_av_VHDL&diff=2738Synthese av VHDL2020-01-30T15:13:38Z<p>Bhu006: </p>
<hr />
<div>===Syntetiseringen av VHDL kode===<br />
<br />
Grunnen til at vi skal syntetisere koden, er at vi må lage beskrivelse av koden tilpassa ein krets.<br />
<br />
Vi vil no prøve å synthesisere vhdl kode. Og etterpå vil vi lage ein testbenk der vi samanliknar utsignala frå den syntetiserte og den opprinnelige koden. Vi bruker ein alu som eksempel.<br />
<br />
==Precision==<br />
<br />
Pass på at lisensen for Quartus er korrekt satt opp, og at Precision finner Quartus.<br />
<br />
Precision bruker Quartus til å syntetisere vhdl-koden. For å starte synteseprogrammet:<br />
<br />
source /eda/mentor/2018-19/scripts/PRECISION_2018.1_RHELx86.sh <br />
precision<br />
<br />
Vel deretter New Project, og deretter Add input file(i dette tilfelle alu_example.vhdl). <br />
Så går vi inn på Setup design, velger ein kretsprodusent, den ønska kretsen og designfrekvens, for eksempel Cyclone V med frekvens 200MHz. For å få ut en vhdl fil av den syntetiserte koden må en gå på Tools->Options->Output og hak av for VHDL og trykk ok.<br />
Trykk så compile, og synthesize. <br />
No kan vi sjå på den generte kretsen i RTL Schematic og Technology Schematic(syntese med den valgte kretsen) under Schematics på venstre side.<br />
<br />
Hvis du får en "ROOTDIR"-error, mangler det en variabel. Skriv følgende i terminalen:<br />
<br />
setenv QUARTUS_ROOTDIR /prog/altera/11.1/quartus<br />
<br />
==Modelsim==<br />
<br />
Start opp Modelsim, lag nytt prosjekt og legg til vhdl fila(alu_example.vhdl). Så legg vi til fila som Precision generte i prosjektdir til 'precision/prosjektnavn_temp_1/prosjektnavn.vhd' (i vårt tilfelle 'alu/add_sub_alu_temp_1/add_sub_alu.vhd').<br />
<br />
Vi trenger simuleringsbibliotek for den valgte kretsfamilien for å kunne simulere etter "Place and Route". Disse bibliotekene kan genereres fra Quartus med menyen Tools > Launch EDA Simulation Simulation Library Compiler.<br />
<br />
Vi har kompilert disse bibliotekene til mappen /prog/altera/vhdl_libs. Du kan "mappe" disse for eksempel slik:<br />
<br />
vmap cyclonev /prog/altera/vhdl_libs/cyclonev<br />
<br />
Deretter legger vi til ei ny vhdl fil der vi skal lage testbenken vår. Vi legger til ein komponent av den opprinnelige og den synthesiserte vhdl koden. Vi koblar alle inngangane til samme signal på testbenken, og gir ut 2 forskjellige utsignal for å samanlikne ved hjelp av assert(sjå fila alu_tb.vhdl). På grunn av at utsignala av dei to komponentane ikkje skifta heilt synkront, testa vi berre kvart nanosekund ved å putta assert inn i ein process med wait for 1ns:<br />
<br />
test : process<br />
begin<br />
wait for 1 ns;<br />
assert (data_out = data_out_synt)<br />
report "Data ut er ulik"<br />
severity Error;<br />
end process test;<br />
<br />
Når vi har laga testbenken, kompilerer vi filene (husk å kompilere i rett rekkefølge med compileorder->autogenerate første gong).<br />
<br />
Siden precision generer samme navn på entityen og architecturen på den syntetiserte filen som i den orginale så vil ikke simulatoren kjøre de samtidig. Dette endres ved å endre entity fra add_sub_alu til add_sub_alu_synth og skifte navnet på architecture fra algoritm til structure øverst og nederst i den syntetiserte filen.<br />
<br />
==Simulering med timing==<br />
<br />
Eksemple på start av simulering med timing:<br />
<br />
vsim -t ps alu_tb -sdfmax :alu_tb:ali=/heim/yngve/vhdl/syntese/alu_temp_1/simulation/modelsim/add_sub_alu_vhd.sdo<br />
<br />
Vi kan sjå at i dei første 50 nanosekunda er utsignala ulike. Dette er fordi før første klokkeflanke er verdiane udefinert i den opprinnelige komponenten, medan den synthesisere ikkje kan ha udefinerte verdiar. I Modelsim vil vi derfor få ein del feilmeldingar dei første 50 nanosekunda.<br />
<br />
==Konklusjon==<br />
<br />
Vi kan teste om den synthesisere komponenten oppfører seg likt med den opprinnelige komponenten ved å koble begge to til samme testbenk. Vi fekk problem i overgangane når vi testa kontinuerlig, så vi løyste problemet ved å berre teste kvart naonosekund. Bortsett frå dei første 50 nanosekunda(sjå grunn over) kan vi sjå at begge komponetane gir ut samme utsignal. Vi prøvde å bruke samme enitynavn på begge komponentane med ulik arcitechture, men fekk berre lov å kompilere og ikkje simulere. Vi kan derfor konkludere med at desse må ha ulike navn.<br />
<br />
==Kode==<br />
<br />
===Kode til alu_example.vhdl===<br />
<br />
<pre><br />
LIBRARY ieee;<br />
USE ieee.std_logic_1164.All;<br />
USE ieee.std_logic_unsigned.all;<br />
<br />
ENTITY add_sub_alu IS<br />
PORT (clk, rst : IN std_logic;<br />
enable_in : IN std_logic;<br />
start : IN std_logic;<br />
enable : IN std_logic;<br />
do_add : IN std_logic;<br />
do_subtract : IN std_logic;<br />
do_hold : IN std_logic;<br />
data_in : IN std_logic_vector(3 DOWNTO 0);<br />
data_out : OUT std_logic_vector (3 DOWNTO 0) BUS);<br />
END add_sub_alu;<br />
<br />
ARCHITECTURE algorithm OF add_sub_alu IS<br />
TYPE states IS (hold, reset, add, subtract);<br />
SIGNAL state_var : states;<br />
SIGNAL reg, int_reg : std_logic_vector(3 DOWNTO 0);<br />
SIGNAL latched_data_in: std_logic_vector(3 DOWNTO 0);<br />
BEGIN<br />
<br />
latch: PROCESS (enable_in, data_in)is<br />
BEGIN<br />
IF (enable_in = '1') THEN<br />
latched_data_in <= data_in;<br />
END IF;<br />
END PROCESS latch;<br />
<br />
fsm: PROCESS (clk, rst) is<br />
BEGIN<br />
IF (rst = '0') THEN<br />
state_var <= reset;<br />
ELSIF (clk'EVENT AND clk = '1') THEN<br />
CASE state_var IS<br />
WHEN hold => IF (start = '1') THEN<br />
state_var <= reset;<br />
END IF;<br />
WHEN reset => IF (do_add = '1') THEN<br />
state_var <= add;<br />
ELSIF (do_subtract = '1') THEN<br />
state_var <= subtract;<br />
END IF;<br />
WHEN add => IF (do_hold = '1') THEN<br />
state_var <= hold;<br />
ELSIF (do_subtract = '1') THEN<br />
state_var <= subtract;<br />
END IF;<br />
WHEN subtract => IF (do_hold = '1') THEN<br />
state_var <= hold;<br />
ELSIF (do_add = '1') THEN<br />
state_var <= add;<br />
END IF;<br />
WHEN OTHERS => state_var <= reset;<br />
END CASE;<br />
END IF;<br />
END PROCESS fsm;<br />
<br />
alu: PROCESS (state_var, latched_data_in, reg)is<br />
BEGIN<br />
CASE state_var IS<br />
WHEN add => int_reg <= reg + latched_data_in;<br />
WHEN subtract => int_reg <= reg - latched_data_in;<br />
WHEN reset => int_reg <= "0000";<br />
WHEN hold => int_reg <= reg;<br />
WHEN OTHERS => int_reg <= reg;<br />
END CASE;<br />
END PROCESS alu;<br />
<br />
mem: PROCESS (clk) is<br />
BEGIN<br />
IF (clk'EVENT AND clk = '1') THEN<br />
reg <= int_reg;<br />
END IF;<br />
END PROCESS mem;<br />
<br />
tri: PROCESS (enable, reg) is<br />
BEGIN<br />
FOR i IN 3 DOWNTO 0 LOOP<br />
IF (enable = '1') THEN<br />
data_out(i) <= reg(i);<br />
ELSE<br />
data_out(i) <= 'Z';<br />
END IF;<br />
END LOOP;<br />
END PROCESS tri;<br />
<br />
END algorithm;<br />
</pre><br />
<br />
===Koden til alu_tb.vhdl===<br />
<br />
<pre><br />
library ieee;<br />
use ieee.std_logic_1164.all;<br />
library work;<br />
use work.all;<br />
<br />
entity alu_tb is<br />
end entity alu_tb;<br />
<br />
architecture struct of alu_tb is<br />
--Deklaring av signal som skal koblast til komponentane.<br />
--Alle innsignal er felles, medan vi har 2 forskjellige utsignal.<br />
signal clk, reset : std_logic;<br />
signal enable_in : std_logic;<br />
signal start : std_logic;<br />
signal enable : std_logic;<br />
signal do_add : std_logic;<br />
signal do_subtract : std_logic;<br />
signal do_hold : std_logic;<br />
signal data_in : std_logic_vector(3 downto 0);<br />
signal data_out : std_logic_vector(3 downto 0);<br />
signal data_out_synt : std_logic_vector(3 downto 0);<br />
<br />
begin<br />
<br />
--Deklarer komponenten alu.<br />
alu : entity add_sub_alu(algorithm)<br />
<br />
--Kobler signala til den opprinnelige komponenten.<br />
port map (<br />
clk => clk,<br />
rst => reset,<br />
enable_in => enable_in,<br />
start => start,<br />
enable => enable,<br />
do_add => do_add,<br />
do_subtract => do_subtract,<br />
do_hold => do_hold,<br />
data_in => data_in,<br />
data_out => data_out);<br />
<br />
--Deklarer komponenten alu_synt.<br />
alu_synt : entity add_sub_alu_synth(structure)<br />
<br />
--Kobler signala til den synthiserte komponenten.<br />
port map (<br />
clk => clk,<br />
rst => reset,<br />
enable_in => enable_in,<br />
start => start,<br />
enable => enable,<br />
do_add => do_add,<br />
do_subtract => do_subtract,<br />
do_hold => do_hold,<br />
data_in => data_in,<br />
data_out => data_out_synt);<br />
<br />
--Klokkegenerator<br />
clock_gen : process<br />
begin<br />
clk <= '0', '1' after 50 ns;<br />
wait for 100 ns;<br />
end process clock_gen;<br />
<br />
--Setter testvektorane.<br />
reset <= '0', '1' after 60 ns;<br />
enable <= '1', '0' after 900 ns;<br />
enable_in <= '1', '0' after 400 ns;<br />
start <= '1', '0' after 300 ns;<br />
do_add <= '1', '0' after 660 ns;<br />
do_subtract <= '0';<br />
do_hold <= '0';<br />
data_in <= X"3";<br />
<br />
--Test process for å samanlikne utsignala kvart nanosekund.<br />
test : process<br />
begin<br />
wait for 1 ns;<br />
assert (data_out = data_out_synt)<br />
report "Data ut er ulik"<br />
severity Error;<br />
end process test;<br />
<br />
end;<br />
<br />
</pre><br />
<br />
[[Category:Mikroelektronikk]]</div>Bhu006http://ift.wiki.uib.no/index.php?title=User:Bhu006&diff=2737User:Bhu0062020-01-30T15:02:04Z<p>Bhu006: Created blank page</p>
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